TMS570LS3137: MIBSPI Slave: Delay configuration in Mater

Kalyan Vagvala61

Part Number: TMS570LS3137

Hello,

As per SPNU499C document page number 1320 Note:

"If in the slave mode of operation and configured in either 3-pin or 4-pin (without SPIENA)

modes, there must be a minimum of 8 VCLK cycles of delay between the last SPICLK and
the start of the SPICLK for the next buffer transmit. In general, this equates to a
VCLK/SPICLK ratio of ≤16 requiring a minimum of 1 SPICLK delay between transmissions."

TMS570LS3137 is configured as slave and in MibSPI mode. we have configured another controller as master with delay is configured based on the above note as per SPNU499C. but we see MSB bit of all 16-bit data is "0". but when we increase delay we could see all the data in master buffer.

VCLK is 20 MHZ.

SPICLK is 5 MHZ.

Delay in Master is 320nSec

Can anyone provide some insight of this behaviour?

Thanks,

Kalyan

over 7 years ago

0 Kalyan Vagvala61 over 7 years ago

Expert 1075 points

Can anyone please help me in this??

0 Kalyan Vagvala61 over 7 years ago in reply to Kalyan Vagvala61

Expert 1075 points

Hi,

Any look at this issue?

Thanks,
Kalyan

0 QJ Wang over 6 years ago in reply to Kalyan Vagvala61

TI__Guru**** 196306 points

Hello Kalyan,

In your setting, the period of the VCLK is 50ns. The minimum delay between the last SPICLK and the current SPICLK should be longer than 8*VCLK cycle = 8*50=400ns.

So your delay setting (320ns) is too small.

0 Kalyan Vagvala61 over 6 years ago in reply to QJ Wang

Expert 1075 points

HI Wang,

Thanks for your response.

with respect to the master where TMS570LS3137 is slave, what could be minimum delay between Chip select assertion and first clock edge?

will this delay matter for TM570LS3137 controller which is acting as slave?

Quick response will be appreciated.

Thanks,
Kalyan

0 Kalyan Vagvala61 over 6 years ago in reply to Kalyan Vagvala61

Expert 1075 points

Adding background to this case:

Master is configured with 320 nSec of delay between Chip select assertion and first clock edge thereby TMS570LS3137 not able to receive multiple packets.

Master configured with 640 nSec of delay between chip select assertion and first clock edge thereby TMS570LS3137 receiving/working fine.

Can you please provide you inputs on how TMS570LS3137 is depending on this delay value?

Thanks,
Kalyan

0 QJ Wang over 6 years ago in reply to Kalyan Vagvala61

TI__Guru**** 196306 points

Hi Kalyan,

Good, it works with a proper delay. this delay defines a setup time for the slave device.

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TMS570LS3137: MIBSPI Slave: Delay configuration in Mater