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CCS/TMS570LC4357: mibspi TMS570LC43x can't receive data

Ciprian Andrei
Intellectual 335 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Tool/software: Code Composer Studio

I'm using two launch pads tms570lc43x and I'm setting one up as a master and the other one as a slave. I used one of you example from the forums as guidance and I'll upload my code down here.

In halcogen for the master configuration I enable master and internal clock whereas for the slave I don't enable master and internal clock. For both configurations I enable only mibspi1 driver from "driver enable ->enable MIBSPI drivers". From PINMUX only the MIPSPI1 and I set the transfer group o for MIBSPI1 with length 16 and chip select cs_0.

Pin setup:

Master      Slave

1SIMO -->1SIMO

1SOMI -->1SOMI

1CS0   -->1CS0

1CLK   -->1CLK

It doesn't work.

3377.MIBSPIslave.zip5078.MIBSPImaster.zip

  • 0
    TI__Mastermind 21425 points

    Hello Ciprian,
    Try to disable all drivers and then enable only MIBSPI1 - on both master and slave. I can see that you have conflicts in pinmux (ball R2) - correct this. Also, set MIBSPI1 Port to fit your needs. Make all pins that are not used in SPI mode to be GIO.
    Something else I can see is that TG0 has 16 buffers and in your code your length is 8.
    In the thread title you are saying that TMS570LC43x can't receive but does master start transferring data?

    Best regards,
    Miro

  • 0 in reply to Miro
    Intellectual 335 points

    This are the configurations that I do now +  the old ones. It won't work, the code is the same.

  • 0 in reply to Ciprian Andrei
    Intellectual 335 points
    I also veryfied the registers for the transfer from "mibspiSetData/mibspiTransfer/mibspiIsTransferComplete" which are set correctly. For instance, in mibspiSetData, my transfer array TX_data is set correctly in the ram memory in mibspiRAM1 through the structure mibspiRAM_t with the *ram pointer. I veryfied with step info the tx[start].data and is set correctly. Also in the mibspiTransfer I veryfied TGCTRL register and is setted with the addresses of my transmitted data. In mibspiIsTransferComplete the TGINTFLG register is also setted and the function returns TRUE. I don't believe is a transferring issues. Cause I also veryfied the same things on the slave and it doesn't receive anything. I think is some configuration in the halcogen that I don't do it correctly.
  • 0 in reply to Ciprian Andrei
    TI__Mastermind 21425 points
    Hi Ciprian,
    Does Master transmitting data?
    MIBSPI1NCS[0] is set as functional in MIBSPI1 Port tab. CS signal you set in MIBSPI1 Transfer Groups to be used for TG0 is CS_0 ( MIBSPI1NCS[0] ) which is exposed on R2. At the same time in PINMUX Tab R2 is set as MIBSPISOMI[1]. You can set CS0 as GIO and use SPI in 3pin mode.
    Please, check wiring on LaunchPad. Could you tell me connector pin numbers, where your cables are connected on LaunchPad (Master or Slave). For example SIMO->J9.6...

    Best regards,
    Miro
  • 0 in reply to Miro
    Intellectual 335 points

    I know that I can use with 3 pin configuration and it works for this matter, but as a next step prior to this I need to control 4 slaves so I need the chip select. Also what mibspics[0] means? *[0] what it refers to? also mibspi1somi[1]. which pin from the board is actually used?

    My pinout at the moment is:

    1CS0 ->  j6.58

    1SIMO->j6.55

    1SOMI->j6.54

    1CLK->j5.53

  • 0 in reply to Ciprian Andrei
    TI__Mastermind 21425 points

    Hi Ciprian,

    For both Master and slave...
    In "MIBSPI1 Port" tab set as follows:
    MIBSPI1 SOMI0 - as functional;
    MIBSPI1 SIMO0 - as functional;
    MIBSPI1 CLK - as functional;
    MIBSPI1 SCS[0] - as functional.
    All other set to GIO.

    In PINMUX tab set R2 as MIBSPI1NCS[0].

    Let me know if it works now.

    Best regards,
    Miro

  • 0 in reply to Miro
    TI__Mastermind 21425 points
    Hi Ciprian,
    Do you have progress?

    Regards,
    Miro
  • 0 in reply to Miro
    Intellectual 335 points

    Hi Miroslav,

    No, I don't have any progress. Still doesn't work.

  • 0 in reply to Ciprian Andrei
    TI__Mastermind 21425 points
    I'll try to recreate your setup. I don't have exactly the same LaunchPad... but let me try.

    Regards,
    Miro
  • 0 in reply to Miro
    Intellectual 335 points
    Okay, thank you.
  • 0 in reply to Miro
    Intellectual 335 points
    why do i use in port's configuration simo[0]. simo[0] etc. if in the pinmux somi[1] muxed when I enable mibspi1. simo[0] and somi[0] I can t even find in pinmux configuration?
  • 0 in reply to Ciprian Andrei
    TI__Mastermind 21425 points
    Hello Ciprian,
    in this thread e2e.ti.com/.../2702260 posted by you I wrote the following:

    "About Master: In PINMUX tab - MIBSPINCS_0 is the only one that needs to be selected for 4 pin mode. All other can be deselected. You can see at device datasheet, Terminal configuration and Function section, that in MIBSPI mode MIBSPI1CLK, MISPI1SIMO[0], MIBSPI1SOMI[0] are not multiplexed (They are not multiplexed with other function. So in PINMUX tab you are not seeing them). MIBSPINCS_0 is multiplexed with MIBSPI1SOMI[1]/ECAP6 and that is why exact function should be selected. As MIBSPI1NENA, MIBSPI1NCS[1..5], are not used (those pins are also set as GIO in MIBSPI1 Tab), we don't need to select them in PINMUX Tab. I have missed to deselect those pins in PINMUX. "

    I think this explanation answers to your last question here as, well.


    Best regards,
    Miro