Hello,
When the PBIST runs (by the function pbistRun), in order to enable the PBIST controller, it sets the register MSTGCR=Ah. Well, since this is the last setting of that register, the field ROM_DIV contained in MSTGCR is set to 0h. It means that the ROM clock source is HCLK divided by 1. PBIST will reset for 16 VBUS cycles. Why is the implemented for-loop with 32 VBUS cycles instead ? (see the corresponding code below)
void pbistRun(uint32 raminfoL, uint32 algomask)
{
volatile uint32 i = 0U;
/* USER CODE BEGIN (17) */
/* USER CODE END */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000005U;
/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;
/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;
/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000000AU;
/* wait for 32 VBUS clock cycles at least, based on HCLK to VCLK ratio */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
/*SAFETYMCUSW 134 S MR:12.2 <APPROVED> "Wait for few clock cycles (Value of i not used)" */
for (i=0U; i<(32U + (32U * 0U)); i++){ /* Wait */ }
...
