EK-TM4C1294XL: ADC1 FIFO results data

Hi Bob,

It seems odd that simply pinning two AINx inputs to +3v3 or GND return different FIFO results data depending on the sequencer step being sampled. Flipping the same two AINx steps GND to +3v3 and the FIFO integer results data may or may not be consistent with the voltage on the AINx. Troubling, a simple static test of sequencers fails without the actual sensor being the analog signal source. Try yourself with EKXL/EVM two 100K series with +3v3 input both AINx channels produce 4095 and half when one AINx=GND. Both AINx=GND step0=-33.2*C, step 1=-30.5*C is roughly 30% accuracy when each LM94022 has +/-2.7*C accuracy (-50-150*C). The two 100K may inject different currents into AINx channels but not to the point it should divide VREFP(AIN9) in half when AIN0=GND. It would be a little difficult to check the application with LM94022 sensor and -30*C. The two FIFO array variables are (int16_t) and do produce the negative sign by default, it was not the application forcing or inserting a negative sign.   The actual sensors (custom PCB) are now within 0.2-0.6*C after adding in an TPTR test to verify the FIFO results matched the sequencer step.     

That is not so consistent behavior between any two channels. When testing for negative integer capability in two steps (0/1). The LM94022 sensor inputs flip testing AINx polarity produces positive integers in both steps below when one of the steps should produce a negative integer as AINx=+3v3. Oddly the positive FIFO integers of any step for the LM94022 sensor is AINx=GND. So we have to pray the LM94022 sensors work better with FIFO step 0/1 than the static testing results below, in your opinion? It didn't even matter if FIFO TPTR index was being properly confirmed (debug) in the test below.

HI Bob,

Perhaps you didn't consider the exact same sequence of events was tested but in opposite order cause the converter to behave differently between any two AINx steps 0 or 1. The 100k's were only used to limit 3v3 into AINx and not even present when GND was direct feed into same AINx. I was using two 3" female jumpers plugged into AINx and two 100k crimped to female pins for the 3v3 BPX headers.

The 3v3/100k produce 33uA CADC charge bias current and the voltage measured 3v2 (via DMM) at the AINx input. The problem is related to the converters ADCSSFSTAT TPTR/HPTR and C+ directives do not correctly POP the FIFO results in a single CPU operation from any given step. I suspect the M4C SAR base structure came from M3 APB beefed up for the M4 to include access via faster AHB which introduced errata into the TPTR of all sequencers being the M3 never had TPTR issues, further explained in the other post.