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TMS570 ADC sampling window configuration.

Abrar Huq21
Intellectual 270 points
Part Number: TMS570LS1227


Hi,

For our project, we are using ADC-1 channels from 0 to 22.
Please could you let me know what values I can give to the register: ADEVSAMP / ADG1SAMP / ADG2SAMP.
Would the following configuration be correct?

SAMPLING_WINDOW_2: ADEVSAMP = 0
SAMPLING_WINDOW_3: ADEVSAMP = 1
SAMPLING_WINDOW_4: ADEVSAMP = 2
SAMPLING_WINDOW_5: ADEVSAMP = 3
SAMPLING_WINDOW_6: ADEVSAMP = 4 and so on.

Thanks.

  • 0
    TI__Mastermind 21425 points
    Hello Abar,
    For ADEVSAMP Register: As stated in TRM (Table 22-32) sampling window (SW) must greater than or equal to 3 ADCLK cycles. But also minimum sampling time has to be taken in account. In Datasheet (Table 7-21) is stated that minimum sampling time for this device is 0.2uS. Also in datasheet minimal Cycle time is stated as 0.033us. If you are using 0.033us as cycle time this means that ADEVSAMP value should be minimum 7 ( 0.2us/0.033us ).

    Best regards,
    Miro
  • 0 in reply to Miro
    TI__Mastermind 49120 points
    Please refer to this application note about ADC source impedance. It details the requirement for calculating the sampling time necessary based on the impedance of the circuit driving the ADC input.

    www.ti.com/.../SPNA118

    Regards,
    Sunil