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TM4C123GH6PM: How to modify the interrupt vector table address in the main program？

Alex824
Intellectual 490 points
Part Number: TM4C123GH6PM

Hi all：

My project uses bootloader and a app with ucosIII. Bootloader I deposited it in flash 0x0 -0x7fff. My app is stored in 0x8000.

But after bootloader jumps to the App entry address, APP is unable to run. I look at some relevant examples.

There is a hint that I need to set interrupt vector table addresses at the entrance of the main program.

For example, MSP430： SCB->VTOR = FLASH_BASE | 0x10000;

For example, STM32:    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x8000);

Is there a similar way for TM4C123 to let me set up the interrupt vector table address in the application? Thank you very much！

  • 0
    TI__Guru 72500 points
    In the TivaWare bootloader examples, this is done in the bootloader before calling the application. See the project "C:\ti\TivaWare_C_Series-2.1.4.178\examples\boards\dk-tm4c123g\boot_serial". In lines 331 through 396 of the assembly language file "bl_startup_ccs.s" you see the bootloader copy the vector table before calling the new application. The project "C:\ti\TivaWare_C_Series-2.1.4.178\examples\boards\dk-tm4c123g\boot_demo1" is an example application that is called from the bootloader. Notice it creates a normal vector table, but in the link command file "boot_demo1_ccs.cmd" the ".intvecs" section is mapped to the application base address instead of to address 0.
  • 0 in reply to Bob Crosby
    Intellectual 490 points
    Thanks for your reply.

    At your prompt, I copied the code in bl_startup_ccs. s about the interrupt vector table to cstatup. c in uCOS III project.

    And modify the interrupt vector table address, my interrupt vector stored in flash 0x8000. UCOSIII can run, I will continue to test, I hope nothing unusual will happen. The code I modified is as follows：

    CPU_VECTOR_TABLE_STORE
    movw r0, #(0x8000 & 0xffff)
    movw r1, #(0xE000ED08 & 0xffff)
    movt r1, #(0xE000ED08 >> 16)
    str r0, [r1]

    ldr sp, [r0]
    ldr r0, [r0, #4]
    bx LR

    static void App_Reset_ISR (void)
    {
    CPU_VECTOR_TABLE_STORE();

    #if __ARMVFP__ /* Enable access to Floating-point coprocessor. */

    HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
    ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
    NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);

    DEF_BIT_CLR(CPU_REG_SCB_FPCCR, DEF_BIT_31); /* Disable automatic FP register content */
    DEF_BIT_CLR(CPU_REG_SCB_FPCCR, DEF_BIT_30); /* Disable Lazy context switch */
    #endif


    __iar_program_start();
    }