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Original question:

TM4C129ENCPDT: TM4C129ENCPDT: Boundary Scan Test Problems on Pin PL7 and Pin PB3

TM4C129ENCPDT: TM4C129ENCPDT: Reset and hold the CPU after Reset via setting register entrys?

user5820349
Prodigy 90 points
Part Number: TM4C129ENCPDT
Other Parts Discussed in Thread: UNIFLASH, SEGGER

Hello,

i would like to perform a software reset and halt the CPU after reset of the IC TM4C129ENCPDT.

 

The programming tool "j-link" which I use describes the procedure as follows:

1. Make sure that the device stops immediately after reset (before it can execute any
instruction of the user application) by setting the VC_CORERESET in the DEMCR.
2. Reset the core and peripherals by setting the SYSRESETREQ bit in the AIRCR.
3. Wait for the S_RESET_ST bit in the DHCSR to become first (reset active) and
then low (reset no longer active) afterwards.
4. Clear VC_CORERESET.

Can someone help me:

Which registers are set to trigger a software reset and halt?
How to get into the "privileged mode"?

Many Thanks

  • 0
    TI__Guru 72500 points

    You probably need to check with Segger to get clarification on that (unless one of the community members knows). I know that on our UniFlash programming tool, the reset and halt is done by default but can be disabled. J-Link is supported by CCS, so it should also work with UniFlash if you have installed CCSv7 or v8, UniFlash and the J-Link drivers.

  • 0 in reply to Bob Crosby
    Prodigy 90 points
    I'm so sorry. Presumably, I did not put the question right.

    What interests me is:
    1) Is there a register that provides a halt the CPU after reset?
    2) What to do to get into "privilege mode"? This is e.g. necessary to set the APINT register on page 178.
  • 0 in reply to user5820349
    Prodigy 90 points
    One more Question:
    Are there any registers that are not described in the datasheet "tm4c129encpdt.pdf"?
    Specifically, I search the registers:

    0xE000EDF0 (ARM Cortex Debug Holding Control and Status Register)
    0xE000EDFC

    Many Thanks
  • 0 in reply to user5820349
    TI__Guru 72500 points
    For a description of the registers that are part of the ARM Cortex M4F processor see the M4 Technical Reference Manual from ARM.
    infocenter.arm.com/.../DDI0439B_cortex_m4_r0p0_trm.pdf
  • 0 in reply to Bob Crosby
    Prodigy 90 points
    Thanks for the hint.
    I also read "ARMv7-M Architectural Reference Manual". So I tried to set the registers as follows (without success):

    DHCSR: 0xE000EDF0 -> 0xA05F0001
    DEMCR: 0xE000EDFC -> 0x01000001
    APINT: 0xE000ED0C -> 0x05FA0001

    The writing of DHCSR and DEMCR registers works. At Register APINT I'm not sure, because I can´t detect a reset and halt.
    Maybe because of "privileged mode" on page 178 to write the register APINT. Do you know how to get and detect if you are in privileged mode?

    Best Regards,
    Ingo Müller