Other Parts Discussed in Thread: HALCOGEN,
Tool/software: Code Composer Studio
I tried to port the example code from spna231.pdf (www.ti.com/.../spna231) from RM48 to TMS570LC43. As far as I can see, the DMA channel for MibSPI5 is the same for both controllers.
I replicated all relevant settings for HALCoGen, and copied the logic from the original project's main to HL_sys_main.
The program compiles and runs but does not start the MibSPI5 communication. I tried to use it with and without ENA functionality.
Settings done in HALCoGen:
Drivers ------- MibSPI5 GIO (for led) MPU --- Enable MPU background region GIO ---- Set GIOB_6 to output (User Led 2) PINMUX ------ MibSPI5 GIOB6 J2 Interupts --------- 33: DMA FTCA on MibSPI5 ------- GLOBAL OVR ON BIT ON DES ON PAR ON TIM ON DLN ON DATA Format 0 Baudrate 20000 Wait for Enable -- if desired Parity enable -- if desired WDELAY 5 Delays 7 5 10 10 Transfer Group 0 Lock Transmission Buffer Mode 5 Lenght 64 Chip Select Hold ON Oneshot transfer OFF PORT SCI 1 SPI -- not used SCI 2 SPI -- not used SCI 3 SPI -- not used SIMO1 DIR OUT SIMO2 DIR OUT SIMO3 DIR OUT
I've attached the ported CCS project to this report.
content of the HL_sys_main.c (same as original main.c, but using a different LED (one from the LaunchXL2 on GIO B 6, instead of one of the HET pins)
/** @file HL_sys_main.c
* @brief Application main file
* @date 07-July-2017
* @version 04.07.00
*
* This file contains an empty main function,
* which can be used for the application.
*/
/*
* Copyright (C) 2009-2016 Texas Instruments Incorporated - www.ti.com
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
*
* Neither the name of Texas Instruments Incorporated nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/* USER CODE BEGIN (0) */
/* USER CODE END */
/* Include Files */
#include "HL_sys_common.h"
/* USER CODE BEGIN (1) */
#include "HL_sys_dma.h"
#include "HL_gio.h"
#include "HL_mibspi.h"
#define LEDPORT gioPORTB
#define LEDPIN 6ul
#pragma DATA_ALIGN(source, 8); /* Note: It is very important to keep the data alignment on 64-bit for the DMA */
static uint16_t source[64];
mibspiRAM_t * const pMibSpiP5Ram = mibspiRAM5;
/* USER CODE END */
/** @fn void main(void)
* @brief Application main function
* @note This function is empty by default.
*
* This function is called after startup.
* The user can use this function to implement the application.
*/
/* USER CODE BEGIN (2) */
/* USER CODE END */
int main(void)
{
/* USER CODE BEGIN (3) */
int32_t i32Index = 0l;
uint16_t ui16Index2 = 0u;
uint16_t ui16Check = 0u;
g_dmaCTRL g_dmaCTRLPKT;
gioInit();
mibspiInit();
mibspiREG5->DMACNTLEN = 0ul; /* Disable Large Count */
mibspiREG5->DMACTRL[0] = ( 1ul << 31) /* Auto-disable of DMA channel (in MibSPIP) after ICOUNT+1 transfers. */
| (63ul << 24) /* Buffer utilized to trigger DMA transfer. */
| ( 0ul << 20) /* RXDMA_MAPx */
| ( 2ul << 16) /* TXDMA_MAPx */
| ( 0ul << 15) /* Receive data DMA channel enable. */
| ( 0ul << 14) /* Transmit data DMA channel enable. */
| ( 0ul << 13) /* Non-interleaved DMA block transfer. This bit is available in master mode only. */
| ( 0ul << 8); /* ICOUNTx */
/* Enable DMA module : this brings DMA out of reset */
dmaEnable();
/* Configure DMA Control Packed (structure is part of dma.c) */
g_dmaCTRLPKT.SADD = (uint32_t)(&source[0]); /* initial source address */
g_dmaCTRLPKT.DADD = (uint32_t)(&(pMibSpiP5Ram->tx[0].data)); /* initial destination address */
g_dmaCTRLPKT.CHCTRL = 0ul; /* channel control */
g_dmaCTRLPKT.RDSIZE = ACCESS_64_BIT; /* read size */
g_dmaCTRLPKT.WRSIZE = ACCESS_16_BIT; /* write size */
g_dmaCTRLPKT.FRCNT = 1; /* frame count */
g_dmaCTRLPKT.ELCNT = (sizeof(source) / sizeof(source[0])) / 4; /* element count */
g_dmaCTRLPKT.ELSOFFSET = 1ul << g_dmaCTRLPKT.RDSIZE; /* element source offset */
g_dmaCTRLPKT.FRSOFFSET = 0ul << g_dmaCTRLPKT.RDSIZE; /* frame source offset */
g_dmaCTRLPKT.ELDOFFSET = 2ul << g_dmaCTRLPKT.WRSIZE; /* element destination offset */
g_dmaCTRLPKT.FRDOFFSET = 0ul << g_dmaCTRLPKT.WRSIZE; /* frame destination offset */
g_dmaCTRLPKT.PORTASGN = 4ul; /* port b */
g_dmaCTRLPKT.TTYPE = FRAME_TRANSFER ; /* transfer type */
g_dmaCTRLPKT.ADDMODERD = ADDR_OFFSET; /* address mode read */
g_dmaCTRLPKT.ADDMODEWR = ADDR_OFFSET; /* address mode write */
g_dmaCTRLPKT.AUTOINIT = AUTOINIT_ON; /* autoinit, on, MIBSPI controls DMA transfers (ICOUNT) */
/* Assign DMA Control Packet to Channel 0 */
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT);
/* Assign DMA request: channel-0 with request line - 8 */
dmaReqAssign(DMA_CH0, 6ul); /* Request Line 6 is MIBSPI5[2], this is MIBSPI5 in buffered mode */
/* Set the DMA Channel 0 to trigger on h/w request */
dmaSetChEnable(DMA_CH0, DMA_HW);
/* Enable Parallel Mode for high data throughput */
mibspiPmodeSet(mibspiREG5, PMODE_4_DATALINE, DATA_FORMAT0);
do
{
static _Bool qFirstLoop = true;
static uint32_t u32Count = 0ul;
ui16Check = 0u;
while(dmaREG->PEND & (1ul << 0) != 0ul)
{
/* Wait till DMA TX transfer has been finished */
}
while(mibspiREG5->DMACTRL[0] & (1ul << 14) != 0ul)
{
/* Wait till DMA TX transfer has been finished */
}
/* Generate some dummy data to send */
for (i32Index = 0l ; i32Index < ((sizeof(source) / sizeof(source[0])) - 1); i32Index++)
{
/* Calculate a checksum for the dummy data packet */
ui16Check += ui16Index2;
source[i32Index] = ui16Index2++;
}
/* Add checksum to the end of the data packet */
source[(sizeof(source) / sizeof(source[0])) - 1] = ui16Check;
/* Enable DMA control in the MIBSPI, this will be auto cleared (Auto-disable of DMA channel Feature) */
/* The first DMA request pulse is generated right after setting TXDMAENAx to load the first transmit data. */
mibspiREG5->DMACTRL[0] |= (1ul << 14); /* Transmit data DMA channel enable. */
if (true == qFirstLoop)
{
while(dmaREG->PEND & (1ul << 0) != 0ul)
{
/* Wait till DMA TX transfer has been finished */
}
/* Trigger MIBSPI transfers */
mibspiTransfer(mibspiREG5, 0ul);
qFirstLoop = false;
}
else
{
/* Do Nothing */
}
if (u32Count % 10000ul == 0ul)
{
gioSetBit(LEDPORT, LEDPIN, !gioGetBit(LEDPORT, LEDPIN));
}
u32Count++;
}
while(1);
/* USER CODE END */
return 0;
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
Symptoms: the program runs through the first main loop, then on the second entry, keeps waiting here:
while(dmaREG->PEND & (1ul << 0) != 0ul)
{
/* Wait till DMA TX transfer has been finished */
}
Nothing happens with the MibSPI5 pins. No CS low, no clock, no data flowing.
My project attached:
