TMS570LS3137: TMS570: CLKTEST: pin clock source valid status polarity

Hello forum,

I am validating the clock tree of a TMS570LS3137 implemtation and i want to check the pin clock source valid status.

Therefore I activate the test in the halcogen function mapClocks:

        systemREG1->SYSPC1 = 1;
        systemREG1->CLKTEST = 0x50101;            

I observe the correct PLL Frequency on ECLK Ball, but I cannot interpret the output of the clock valid pin (SEL_GIO_PIN > PLL1 valid status)

+ Q: Is the Pin GIOB[0] (Ball M2)(see section 2.5.1.31; SEL_GIO_PIN Field description of the TRM SPNU499C) or  NHET1[12] (Ball B4) (section 2.4.4 of the TRM) the correct terminal to observe?

+ Q: What is the polarity of a valid status? (LOW/HIGH)?

+ Q: Is there a kind of Output Enable necessary to obsere the clock valid status?

regards

Lorenz