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TMS570LS3137: Architecture protections for detection of single and multiple bit upsets

Brian White69
Prodigy 10 points
Part Number: TMS570LS3137

I'm evaluating the TMS570LS3137 and it's use in a safety critical application. Specifically I'm looking at the datapaths in the design to evaluate the risk of undetected erroneous data or loss of availability.

is the intended operation to run out of flash or to have the program load from flash and then run out of SRAM? Also does each processor have the option for independent data paths to both flash and SRAM? figure 1-1 depicts a single path while figure 6-10 depicts what looks like a true redundant data path to separate RAM banks for each processor. Is there an application note that explains what aspects the lockstep function protects from?

Also is there any fast nuetron test data for the device? The best I could find is here:

e2e.ti.com/.../1883563

I am interested in the actual test procedure that was used and how rate was determined. There is a chance I will be testing this device in a fast neutron facility so if there is any pre-canned test software available I would be very interested in that. I'll be looking to measure flash, SRAM, flop rates and SEL. 

  • 0
    TI__Mastermind 49120 points

    Hi Brian,

    See my answers embedded in the sections below.

    Is the intended operation to run out of flash or to have the program load from flash and then run out of SRAM?

    >> The application program typically loads into and runs out of flash memory. SRAM is used for stacks, for the CPU scratchpad, and for temporary variables.

    Also does each processor have the option for independent data paths to both flash and SRAM? figure 1-1 depicts a single path while figure 6-10 depicts what looks like a true redundant data path to separate RAM banks for each processor.

    >> Only one of the two CPUs' outputs are connected to the interconnect. Figure 6-1 shows that the tightly-coupled memory interface for the SRAM (BTCM) is split into two parallel interfaces (B0TCM and B1TCM). These interfaces are 64-bit interleaved to allow for multiple masters to access the SRAM without causing arbitration conflicts.

    Is there an application note that explains what aspects the lockstep function protects from?

    >> There isn't an application note specific for the lock-step function. Every CPU output is compared on each cycle to the second CPU's output. The safety manual describes the importance of this diagnostic mechanism in more detail.

    Also is there any fast neutron test data for the device? The best I could find is here:

    e2e.ti.com/.../1883563

    I am interested in the actual test procedure that was used and how rate was determined. There is a chance I will be testing this device in a fast neutron facility so if there is any pre-canned test software available I would be very interested in that. I'll be looking to measure flash, SRAM, flop rates and SEL. 

    >> That is the best data we have. We can provide information about the test procedure. Usually this kind of information is shared via the semi-private forum here: 

    Access to this forum requires a safeTI NDA between TI and your organization. You can request an NDA here () if you don't already have one.

    Regards,

    Sunil