Part Number: EK-TM4C1294XL
Hi All,
It would seem LM flash programmer is considered USR privilege during flash writes upon certain registers when the MPU has been enabled for debug register NMI review. Configuring NVIC_MPU_ATTR register (prv: RW, USR=None somehow causes sudden MCU death after flash writes with reset MCU (after programming box checked) but only upon certain application execution. Clicking LMFlash hardware reset button after MCU crash (2nd SOFTRST) clears the crashing event condition until the next firmware update. After MCU can POR all day without application crashing if you don't update firmware again. The reason behind granting software privilege RW access seemingly is security based, in my mind we should not grant USR (hacker) any such privilege.
Giving full Cortex-M USR software RW privileges stops application runtime sudden death syndrome! Perhaps why some peripheral errata issues are perceived as POR related events when the registers are not being configured, if or when ever USR (none) issues a SFTRST?
/* Enable the Cortex-M memory protection unit. PRIV_DEFAULT: * Enables the default memory map when in privileged mode and * when no other regions are defined. HARDFLT_NMI: Enables * the MPU while in a hard fault or NMI exception handler. * If this option is not enabled, then the MPU is disabled while * in one of these exception handlers and the default * memory map is applied. */ MAP_MPUEnable(MPU_CONFIG_PRIV_DEFAULT | MPU_CONFIG_HARDFLT_NMI); /* MPU attributes Software privileged mode, RW full access */ HWREG(NVIC_MPU_ATTR) = NVIC_MPU_ATTR_AP_RW_RW; //NVIC_MPU_ATTR_AP_RW_NO 0x01000000 (prv: rw, usr: none) //NVIC_MPU_ATTR_AP_RW_RW 0x03000000 (prv: rw, usr: rw)
