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TMS570LS1224: Issue on configuring SPI communication (delay, polarity)

audry kouanda
Prodigy 220 points
Part Number: TMS570LS1224
Other Parts Discussed in Thread: HALCOGEN

Hello,

I am using a TMS570LS1224 µC in a project, and have to interface it with several sensors including an ADIS16210 from AnalogDevice ( )

I have issues with the SPI communication, and I would like any help on it :-)

1) As you can see in the ADIS16210 datasheet page 7 of 20: the clock configuration required is Polarity = 1, Phase = 1. I configured this (with halcogen), but it did not work. Later, giving more attention to chronograms on page 8 of 20 of this datasheet, and comparing to the descriptions and chronograms of the page 588/589 of the TMS570 techmanual, I realized that the correct configuration seems to be Polarity = 1 and Phase = 0. My qyestion is: why such a difference between the configuration given in the sensor datasheet and the actual working confiugration ont µC ? I thought Phase en Polarity where standaradised parameters, with same behaviour for same values ?

2) When i switched from POL/PHASE = 11 to POL/PHASE = 1/0, it works better but still not perfectly: sometimes I miss data and dont know why... I'm gonna have a look on a scope, but something retained my attention: on the sensor datasheet, it is specified that de delay between 2 SPI transaction must be at least of 40µs. I wanted to program it in halcogen, using the wdelay parameter but here is my problem: the wdelay is computed dividing the VCLK1 frequency by a 8 bits prescaler. With a VCLCK of 80Mhz, I can't reach 40µs of delay, but only something around 2µs..

I went to the clock tree parameter and downed the VCLCK1 frequency to 10 MHz (minimum), but then the maximum prescaler value in halcogen is 63, wich leads to a wdelay of 6.5µs: this is way too short for the communication. Any clue what I am supposed to do ? For now I do 1 transaction, wait for 100 µs at least  (using freeRTOS) and then do the second transaction, but I would like to have something cleaner.

Now :

spiTransmitData(spiREG3, &(Accelerometer->spi_conf_register), 1, TxData);
 vTaskDelay(20);
spiReceiveData(spiREG3, &(Accelerometer->spi_conf_register), 1,  RxData);

and I'd like to do

spiTransmitAndReceiveData(spiREG3, &(Accelerometer->spi_conf_register), 2,  TxData,  RxData); respecting the correct wdelay

Thanks

  • 0
    TI__Mastermind 21425 points
    Hello,
    I have looked on ADIS16210 device datasheet and according to diagrams, the Master device (TMS570LS1224) should use Polarity = 1 and Phase = 0.
    Delay that could be applied by WDELAY (SPIFMT[31:24]) is WDELAY*Pvclk + 2*Pcvlk (where Pvclk is VCLK period). For 10MHz this is 12.9uS.
    In case you need 40uS you should add other than WDELAY or manage CS manually.
    Best regards,
    Miro
  • 0 in reply to Miro
    Prodigy 220 points

    Hello, thanks for your answer !
    1) For now I manage the delay using vTaskDelay(20); function from FreeRTOS. But what do you mean by "In case you need 40uS you should add other than WDELAY" ? Is there a way to do so without manually managing CS ?

    2) Also: downing the VCLCK1 (using clock tree prescaler) from 80MHz to 10MHz solved the data miss issue: I now get consistent data on the spi. But I would like to understand why, as even when I had VCLCK1 at 80Mhz, the SPI clck was set to 500KHz using the prescaler). I mean: the only thing that changed beteween setting VCLCK1 from 80Mhz to 10MHz is the prescaler, but the output spi clck was 500KHz in both case (checked with oscilloscope)... so I would have expected the same behaviour in communication ?

  • 0 in reply to audry kouanda
    TI__Mastermind 21425 points
    Hello,
    1) I meant the same as you did with vTaskDelay function;
    2) I expect same behavior too if delay you add is at least 40uS (as stated in slave device datasheet) in both cases. I am wondering whether FreeRTOS is not interfere somehow.

    Best regards,
    Miro