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TMS570LC4357: nERROR and nERROR1 Input Multiplexing

Part Number: TMS570LC4357


Hello,

We are using the TMS570LC4357,  we would like more information about the IOMM module.

In Table 6-3 and Figure 6-8 of Reference manual (spnu563a), ESM1 register can sample nERROR or nERROR1 via PINMMRx.

Nevertheless, in thefollowing sentence is confusing for us:

"By default, the ESM1 Error Pin Status Register (ESMEPSR) samples the nERROR pin input. The default is achieved with PINMMR174[16] = 1. By setting PINMMR174[16] = 0, the ESM1 Error Pin Status register
will sample from the nERROR1 pin instead"

> In Table 4-20 of datasheet, what the differences between nERROR (from ESM error) on pin B14 and nERRO (from ESM error 1) on pin J2 ?

> The reference manual mention the nERRO pin and the nERROR1 pin but this is not the case of datsheet where nERROR is on J2 and B14.  Could you clarify that please ?

>  Moreover, Why ESM1 sample nERROR pin input altough this is an output and not an input as mentionned in the refrence manual ?

Best regards,

Christopher

  • Hello Christopher,

    I understand the confusion caused by the unclear documentation. Originally there was a plan to offer these parts in either a lock-stepped or a split-lock configuration. This is no longer the plan, and only lock-stepped cores are supported.

    In the split-lock configuration, the two R5 cores would operate independently. There were also two separate ESM modules, one corresponding to each core. These two ESM modules would have their own separate error terminals: nERROR1 and nERROR2. There was also another nERROR terminal that would just be (nERROR1 AND nERROR2).

    Given the above information, it is easier to explain the muxing. There is only ESM1 available for a lock-stepped configuration. So nERROR1 and nERROR are essentially the same (nERROR2 is always High) from an output function point of view. In terms of the terminal assignments, nERROR is available on terminal B14 while nERROR1 is available as a multiplexed option on terminal J2. Please always configure PINMMR174[16]=1, which is also the default case. Switching the error signal input to the ESMPSR (Error pin status register) could result in you reading the status of the GIOB[6] output, which is not desirable.

    We will update the IOMM chapter to remove information about ESM1/2 as well as nERROR1/2 to avoid confusion.

    Regards,
    Sunil