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TMS570LS3137: Port configuration for the SPI5

Niveditha Bangalore
Prodigy 120 points

Part Number: TMS570LS3137

Using the AUTOSAR_MCAL_TMS570LSx-05.30.00. The Issue is related to the Port Configuration for the SPI5. A Peripheral device is connected to MIBSPI5. The following pins are used

MIBSPI5SIMO[0](Pin99), MIBSPI5SOMI[0](Pin 98), MIBSPI5CLK(Pin100), MIBSPI5NCS[0](Pin 32). These Port Pins are set to SPI mode in the Port Configuration.

Checked the generated code of Port_Pbcfg.c for the SPI5 Port pins. If PortPinSpi5_10( MiBSPI5SOMI0) is set to Mode SPI in the Port Configuration, SPIPC0 bit 24 is set.
If PortPinSpi5_6(MiBSPI5SIMO0) is set to Mode SPI in the Port Configuration, SPIPC0 bit 16 is set.
But for all the other SPI ports like eg., SPI3 if the PortPinSpi3_8(MiBSPI3SIMO)  SPIPC0 bit 10 is set and PortPinSpi3_9 ( MiBSPI3SOMI ) SPIPC0 bit 11 is set for the SPI Mode.

Why only for SPI5, bit 16 and 24 are set for SIMOFUN0 and SOMIFUN0? I tested with setting bit 10 and 11 in the Port_PBcfg.c then the SPI5 works.
Please check the generated code for the Port for the SPI5.

  • 0
    TI__Guru**** 199466 points
    Hello Niveditha,

    I will check the MCAL and come back to you soon.
  • 0 in reply to QJ Wang
    TI__Guru**** 199466 points
    Hello Niveditha,

    Bit 24 and Bit 16 of SPIPC0 are mirroe of bit 11 and bit 10. Bit 24 and bit 16 are not physically implemented. Any write to bit 24 and bit 16 will be reflected on bit 11 and bit 10. When bit 24 and bit 11 are simultaneously written, the value of bit 11 will control the SPISOMI[0] pin. When bit 16 and bit 10 are simultaneously written, the value of bit 10 will control the SPISIMO[0] pin.
  • 0 in reply to QJ Wang
    Prodigy 120 points

    Hi,

    Thanks!

    Bit 24 and Bit 16 of SPIPC0 are mirroe of bit 11 and bit 10. Bit 24 and bit 16 are not physically implemented.

    -- OK.

    Any write to bit 24 and bit 16 will be reflected on bit 11 and bit 10. When bit 24 and bit 11 are simultaneously written, the value of bit 11 will control the SPISOMI[0] pin.

    -- Yes. This is what is mentioned in the Technical Reference Manual. However, my observation is any write to bit 24 and bit 16 is not reflected on bits 11 and bit 10 respectively. I have verified this also by manually writing into the SPIPC0 register in the debugger. But in the debugger, a write to bit 10 and 11 automatically updates the bits 16 and 24. SPI5 for my requirement { MIBSPI5SIMO[0](Pin99), MIBSPI5SOMI[0](Pin 98), MIBSPI5CLK(Pin100), MIBSPI5NCS[0](Pin 32)} works only if the bits 10 and 11 are set. Please check the code generation for Port_PBcfg.c for SPI5 Port container. 

    Additional information, this is observed only for SPI5 and works fine for SPI3 port for eg., Port configuration for SPI3 Port to use SPISOMI[0] and SPISIMO[0] pins generate code where bits 10 and 11 are set.

    See the generated code of Port_PBcfg.c and the register values too.

    Regards

    Niveditha

  • 0 in reply to Niveditha Bangalore
    Prodigy 120 points
    Hi Wang,

    Do you have some inputs for me on this? Or do you need some inputs from me?

    Regards
    Niveditha
  • 0 in reply to Niveditha Bangalore
    TI__Mastermind 19395 points

    Hi Niveditha,

    Your observation is correct. Writing to bits 16 and 24 does not get reflected in bits 10 and 11. Code has to be modified to write to correct bit positions. We will take this bug report and enter in to our internal tracking tool.