TMS570LC4357: Peripheral power down mechanism

Etienne Alepins

Part Number: TMS570LC4357

Hi,

This question is related to .

The other thread explained that when accessing to a peripheral whose clocks were disabled using PCR registers, then the peripheral's clock would be temporarily re-enable to allow the access to be completed. Will the same occur if the clock domain in which the peripheral is was disabled? (using SYS.CDDIS register)

Thanks.

over 7 years ago

0 QJ Wang over 7 years ago

TI__Guru**** 198766 points

Hello Etienne,

I will read the previous threads and come back to you later today.

0 QJ Wang over 7 years ago in reply to QJ Wang

TI__Guru**** 198766 points

Hello Etienne,

When the peripheral is powered down using PCR register (PSPWRDWNSETx), the clock (VCLKx) to the module is gated. When CPU accesses the module, the peripheral clock will be enabled and the module will be waked up for several clock cycles.

When the clock domain is disabled, CPU and DMA will not be able to access this module.

0 Etienne Alepins over 7 years ago in reply to QJ Wang

Intellectual 775 points

Hi,

Ok, but then, accessing from the core a peripheral whose clock domain has been disabled will result in what behavior? Transaction ignored? Data Abort? Corruption of the CPU internal state?

Thanks.

0 QJ Wang over 7 years ago in reply to Etienne Alepins

TI__Guru**** 198766 points

Hello Etienne,

I want to use SCI as an example. If the bit[24] of PSPWRDWNSET0 is set, the SCI is in power down mode. The CPU still is able to read/write the SCI register, but the module is in IDLE mode, module is not able to TX and RX data. No data abort or corruption, but the code will stuck at a while() loop checking SCI_FLR.

0 Etienne Alepins over 7 years ago in reply to QJ Wang

Intellectual 775 points

Hi,

That doesn't answer my question. Let's indeed take the example of the SCI3. Let's say bit 24 of PSPWRDWNSET0 is NOT set (i.e. peripheral is ACTIVE), but now let's disable VCLK clock domain by setting SYS.CDDIS[VCLKPOFF](2) to 1. Now, what will be the behavior if an SCI register is read or written? (e.g. SCI_FLR).

Thanks,
Étienne

0 QJ Wang over 7 years ago in reply to Etienne Alepins

TI__Guru**** 198766 points

Hello Etienne,

If the clock domain (VCLK1) is turned off, the CPU will not be able to access SCI registers at all.

0 QJ Wang over 7 years ago in reply to QJ Wang

TI__Guru**** 198766 points

BTW, accessing those registers will generate data abort.

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TMS570LC4357: Peripheral power down mechanism