CCS/TM4C1294NCPDT: TM4C1294XL SSI DMA DMA_TX does not initiate

Part Number: TM4C1294NCPDT

Tool/software: Code Composer Studio

Hi Team,

TM4C is as a SSI slave and other peripheral as master. Based on Slave ready, a gpio signal is initiated to the master for SPI communication.

With DMA configuration as added below, data transfer from on MISO line does not initiate and the mode does not change to UDMA_MODE_STOP mode after initializing the ROM_uDMAChannelTransferSet.

ui32Mode = uDMAChannelModeGet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT);
if(ui32Mode == UDMA_MODE_STOP)
{
        SLAVE_READY();
}

Here is the snippet initialization of SPI and DMA configurations, MasterReadyIntHandler handler is configured to a gpio line from the SPI master MCU.

//*****************************************************************************
//
// Interrupt handler from master for data ready
//
//*****************************************************************************
void
MasterReadyIntHandler(void)
{
    uint32_t ui32Status;
    ui32Status = ROM_GPIOIntStatus(GPIO_PORTN_BASE, 1);    
    if (GPIO_PIN_5 & ui32Status)
    {
        ROM_GPIOIntClear(GPIO_PORTN_BASE, GPIO_PIN_5);
        ROM_SSIDisable(BLE_SSI_BASE);
        ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT,
                                   UDMA_MODE_BASIC,
                                   (void *)(SSI0_BASE + SSI_O_DR),
                                   g_ui8SSIRxBuf,
                                   8);
        ROM_uDMAChannelTransferSet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT,
                                   UDMA_MODE_BASIC,
                                   fft_out,
                                   (void *)(SSI0_BASE + SSI_O_DR),
                                   8);    // sizeof(fft_out)
        uDMAChannelAssign(UDMA_CH11_SSI0TX);
        uDMAChannelEnable(UDMA_CH11_SSI0TX);
        uDMAChannelAssign(UDMA_CH10_SSI0RX);
        uDMAChannelEnable(UDMA_CH10_SSI0RX);
        ROM_SSIEnable(BLE_SSI_BASE);

    }
}

void SSI0_DMA_Init(void)
{
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_SSI0);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);

	ROM_SysCtlPeripheralDisable(SYSCTL_PERIPH_UDMA);
	ROM_SysCtlPeripheralReset(SYSCTL_PERIPH_UDMA);
	ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_UDMA);
	ROM_SysCtlDelay(10);

	ROM_IntEnable(INT_UDMAERR);

	//
	// Point at the control table to use for channel control structures.
	//
	ROM_uDMAControlBaseSet(pui8ControlTable);

	GPIOPinConfigure(GPIO_PA2_SSI0CLK);
	GPIOPinConfigure(GPIO_PA3_SSI0FSS);
	GPIOPinConfigure(GPIO_PA4_SSI0XDAT0);
	GPIOPinConfigure(GPIO_PA5_SSI0XDAT1);

	ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_2);
	ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_3);
	ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_4);
	ROM_GPIOPinTypeSSI(GPIO_PORTA_BASE, GPIO_PIN_5);

	MAP_GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_2,
						 GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD_WPU);
	MAP_GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_3,
						 GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
	MAP_GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_4,
						 GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);
	MAP_GPIOPadConfigSet(GPIO_PORTA_BASE, GPIO_PIN_5,
						 GPIO_STRENGTH_4MA, GPIO_PIN_TYPE_STD);

	/* Configure the SSI0 port */
	ROM_SSIConfigSetExpClk(BLE_SSI_BASE, g_ui32SysClock,
						   SSI_FRF_MOTO_MODE_0, SSI_MODE_SLAVE, 8000000, 8);
	//ROM_SSIAdvModeSet(BLE_SSI_BASE, SSI_ADV_MODE_READ_WRITE);
	ROM_SSIAdvModeSet(BLE_SSI_BASE, SSI_ADV_MODE_LEGACY);

	ROM_SSIEnable(BLE_SSI_BASE);
	
	// Slave ready pin initialization
    ROM_SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
    while(!ROM_SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOH))
    {
    }
    ROM_GPIOPinTypeGPIOOutput(GPIO_PORTH_BASE, GPIO_PIN_2);
    MAP_GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_2,
                         GPIO_STRENGTH_8MA, GPIO_PIN_TYPE_STD);
					
    //****************************************************************************
    //uDMA Init
    //****************************************************************************
					
	SSIDMAEnable(SSI0_BASE, SSI_DMA_RX | SSI_DMA_TX);

    //****************************************************************************
    //uDMA SSI0 RX
    //****************************************************************************

    //
    // Put the attributes in a known state for the uDMA SSI0RX channel.  These
    // should already be disabled by default.
    //
    ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI0RX,
                                    UDMA_PRI_SELECT |
                                    (UDMA_ATTR_HIGH_PRIORITY |
                                    UDMA_ATTR_REQMASK));

    //
    // Configure the control parameters for the primary control structure for
    // the SSIORX channel.
    //
    ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI0RX | UDMA_PRI_SELECT,
                              UDMA_SIZE_8 | UDMA_SRC_INC_NONE | UDMA_DST_INC_8 |
                              UDMA_ARB_4);
    

    //****************************************************************************
    //uDMA SSI0_BASE TX
    //****************************************************************************

    //
    // Put the attributes in a known state for the uDMA SSI0TX channel.  These
    // should already be disabled by default.
    //
    ROM_uDMAChannelAttributeDisable(UDMA_CHANNEL_SSI0TX,
                                    UDMA_PRI_SELECT |
                                    UDMA_ATTR_HIGH_PRIORITY |
                                    UDMA_ATTR_REQMASK);

    //
    // Set the USEBURST attribute for the uDMA SSI0TX channel.  This will
    // force the controller to always use a burst when transferring data from
    // the TX buffer to the SSI0.  This is somewhat more effecient bus usage
    // than the default which allows single or burst transfers.
    //
    ROM_uDMAChannelAttributeEnable(UDMA_CHANNEL_SSI0TX, UDMA_ATTR_USEBURST);

    //
    // Configure the control parameters for the SSI0 TX.
    //
    ROM_uDMAChannelControlSet(UDMA_CHANNEL_SSI0TX | UDMA_PRI_SELECT,
                              UDMA_SIZE_8 | UDMA_SRC_INC_8 | UDMA_DST_INC_NONE |
                              UDMA_ARB_4);

}

Please let me know if I am on correct understanding of using DMA.

Best Regards,

Kiran