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TMS570LC4357: Clock Test Mode

Christopher TRITANT
Expert 1080 points
Part Number: TMS570LC4357

Hello,

We have questions about derived clocks on TMS570 . In Datasheet (SPNS195C) Table 6-18. Clock Test Mode Options for Signals on ECLK1, it is mentioned that clock test mode is accessible on ECLK1.

1- Is it possible to check these clocks on ECLK2 :
- Oscillator clock?
- GCLK1 clock?
- HF LPO clock?
- VCLK clock?
- VCLK3 clock?
- RTI Base clock?
- Flash HD Pump Oscillator clock ?

If Yes, is it the same access that  ECLK1?

2- Is it possible to apply a division factor for the following clocks :
- GCLK1 clock with a division factor of 10?
- VCLK with a division factor of 5?
- VCLK3 with a division factor of 5?
- Flash HD Pump Oscillator with a division factor of 6?

What are the registers to use for these divisions?

Best regards,

Christopher

  • 0
    TI__Guru**** 196736 points
    Hello Christopher,

    The ECLK1 supports clock test mode, but ECLK2 doesn't. ECLK1 can output GCLK/VCLK3/LPO/..., but ECLK2 only outputs clock derived from VCLK1 or OSCIN. ECLK2 functionality can be enabled by writing 5h to the ECP_KEY field of the ECPCNTL1 register.

    The ECLK2 clock source is defined by ECPSSEL bit in ECPCNTL1 register, and the divider is defined by ECPDIV field of the ECPCNTL1. There are only 2 clock source for ECLK2: VCLK1 and OSCIN.

    SYSPC[9:1] are used for both ECLK1 and ECLK2.
  • 0 in reply to QJ Wang
    Expert 1080 points

    Hello,

    Thanks for your answer.

    Could you tell us that for the SEL_ECP_PIN bit in ECLK pin clock source select, Oscillator clock stands for OSCIN (as for ECLK2 clock source) ?

    Best regards,

    Christopher

  • 0 in reply to Christopher TRITANT
    TI__Guru**** 196736 points
    Hello Christopher,

    You are correct. The Oscillator clock in Table 6-18 (spns195c.pdf) is OSCIN.