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TMS570LC4357: SCI/LIN GIO functionality

Christopher TRITANT
Expert 1080 points
Part Number: TMS570LC4357


Hello,

We are currently using the TMS570LC4357 and we have some questions about the SCI/LIN function.

There are two reset in these modules: Global Reset (RESET bit in SCIGCR0 register) and software reset (SWnRST bit in SCIGCR1 register).

What is the best means to deactivate the SCI/LINfunctionality (blocking of transmission and reception) and used GIO functionality in addition of SCIPIO0 register configuration ?

- Shall we release the global reset and maintain the Sw reset to reset state machine of SCI/LIN module

or

- Shall we release the global reset and the Sw reset of SCI/LIN module and disable the transmission and reception via TXENA and RXENA bits of SCIGCR1 register ?

Best regards,

Christopher

  • 0
    TI__Mastermind 49120 points
    Hi Christopher,

    The RESET bit in SCIGCR0 holds the module under reset. No communication activity is possible in this case. You can also not configure the module for any communication. So if you don't plan to use this module for any activity, keep this RESET bit in its default state (0).

    You can also disable the peripheral clock to this module by setting the correct bit in the PSPWRDWNSET (Peripheral Select Power Down Set) register. For the TMS570LC43x MCUs, this is bit 6. This would cause even an accidental write to the register frame to cause a data abort.

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Expert 1080 points
    Hi Sunil,

    Thanks four your answer.
    And if we plan to use the GIO block in the SCI/LIN module, the RESET assertion will reset also the GIO functionality of this module, is it correct ?
    So, if we want to use the GIO functionality, How ensure that No communication will be performed and only GIO functionality will be performed on SCI/LIN module ?

    Best regards,
    Christopher
  • 0 in reply to Christopher TRITANT
    TI__Mastermind 49120 points
    Hi Christopher,

    The SWnRESET bit in SCIGCR1 enables you to keep the TX and RX state machines under reset. This does not affect the GPIO functionality of the SCI terminals. The module needs to be out of reset (SCIGCR0 = 1) and the peripheral clock to the module must be enabled via the PSPWRDWNCLR.6 register bit.

    Regards,
    Sunil