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TMS570LS3137: TMS570LS3137: TMS570LS3137 MIBSPI slave in Multi-buffer Configuration

Kalyan Vagvala61
Expert 1075 points
Part Number: TMS570LS3137


Hello,

This question is continuation of the discussion in below thread:

https://e2e.ti.com/support/microcontrollers/hercules/f/312/t/747086

We have TMS570LS3137 configured in salve mode and MibSPI enabled. We have below scenario in my code

1. Set MibSPI Tx data using "mibspiSetData".
2. Enable TGENA bit for transmission.
3. Set MibSPI Tx data using "mibspiSetData". (Not sure by this time previously set of data is sent)
4. Enable TGENA bit for transmission.

After above steps we are not observing "INTFLGRDY" field of TGINTFLG register is not set . is this expected in this case.

do you have any suggestion to handle this case?

Thanks,
Kalyan

  • 0
    TI__Mastermind 21425 points
    Hello Kalyan,
    I have forwarded this thread to one of our MIBSPI experst!

    Due to the US holiday the responses may be delayed until the week of November 26th.

    Best regards,
    Miro
  • 0 in reply to Miro
    TI__Guru**** 197426 points
    Hi Kalyan,

    In your case, the MibSPI1 is used as a slave. MibSPI receives the clock from the external master for transferring the data. If SPIENA pin is used, MibSPI can drive SPIENA low to allow the master SPI to drive the clock pulse stream. In slave side, the CS signal is used as a trigger.