• State TI Thinks Resolved
  • Locked Locked
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 30 subscribers
  • Views 424 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LC4357: L2FMC#5 - clarification of used terms for modules and access into those modules

Jiri Janacek
Genius 3315 points
Part Number: TMS570LC4357

Hi all,

may you explain some namings used in the Silicon Errata SPNZ232B for the errattum item L2FMC#5 Incorrect data read from flash ECC data memory region, flash OTP memory region, or data flash memory region when configured as "normal" type memory?

This issue is related to the following modules / peripherals. Are attached sentences right or do I have a wrong idea about that?

  1. ECC data memory
    1. this region is accessed by the CPU - so by a user SW (actually by the TI F021 library code) - only during the uploading of such SW, yes? So that's the write access that shouldn't be affected by this issue, right?
    2. otherwise this region is accessed by the internals (built-in HW modules) when code and data are read
    3. to the item b.: additional to the ECC check when data is read from the flash memory and transferred via the internal bus, there is a (other-side) check of the ECC that is performed by the internals when data enters the CPU; in other words, ECC data memory is accessed during every instruction load (fetch), so there should be sufficient to configure the MPU region for the code flash memory. But that would lead to a huge performance penalty for program execution.
  2. flash OTP memory
  3. data flash memory
    1. is this another naming for the EEPROM emulated above the dedicated flash memory space (0xF0200000 - 0xF021FFFF)?
Thanks for your hints in advance,
Best regards, Jiri
  • 0
    TI__Guru**** 196416 points
    Hello Jiri,

    1. Flash data space ECC (0xF040_xxxx)
    a. Write access is not affected
    b. Only read from this region is affected
    c. reading code flash (0x00000000~0x003FFFFF) is not affected. This flash area can be configured as normal, device, or strongly-ordered.
    2. Flash OTP: 0xF000_0000 ~ 0xF00C_1FFF
    3. Data flash memory or EEPROM bank: 0xF020_xxxx, and data flash ECC or EEPROM ECC: 0xF010_xxxx
  • 0 in reply to QJ Wang
    Genius 3315 points

    Hi QJ Wang,

    thanks for your precise answer - that explains me a lot!

    Just the last question(s):

    • I'm not aware of a case that our code would deliberately read the flash ECC area - honestly spoken, I don't know why it should be ;-) Am I right?
      • e.g. SPNU540a: ECC evaluation is done by the ECC control logic inside the bus master or the CPU
        Interconnect Subsystem.
      • so why should this area be directly addressed and read by CPU itself?

    Thanks for your clarification in advance,

    Best regards, Jiri

  • 0 in reply to Jiri Janacek
    TI__Guru**** 196416 points
    Hello Jiri,

    Deliberate single-bit and double-bit errors have been placed in the OTP for checking the L2FMC ECC functionality. Any portion of the 64 bits in TI OTP bank 0 location 0xF008_03F0 through 0xF008_03F7 will generate a single-bit error. Any portion of the 64 bits in TI OTP bank 0 location 0xF008_03F8 through 0xF008_03FF will generate a double-bit error.

    The values at those location is fixed. The ECC value with 1-bit error and 2-bit error have been programmed into their ECC area. When CPU read 64-bit data from 0xF008_03F0, it also read the corresponding ECC. Upon receiving the data and the ECC, the CPU will evaluate the integrity of the data by performing the ECC check.