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TMS470 Loop resolution clock

Other Parts Discussed in Thread: TMS470R1B1M

Hi guys

Here is a example code in which the timer is used to trigger the ADC at 10 ms. I've run this code and the clock is right 10ms. However, i dont know how to obtain this clock, as LR Div = 8, HR Div = 10 and SYSCLK = 58.9824MHz. In my opinion, the clock for interrupt should be calculated by SYSCLK /(LRDIV * HRDIV) = 59MHz / 80. How does 10ms come from?

Thanks a lot

Here is the code

#include <intrinsic.h>
#include "iotms470r1b1m.h"
#include "tms470r1b1m_bit_definitions.h"
#include "std_het.h"
#include "tms470r1b1m_HET_INT_02_H.h"

void MemCopy32(unsigned long *dst, unsigned long *src, int bytes);

__no_init volatile HETPROGRAM0_UN e_HETPROGRAM0_UN @ 0x00800000;

volatile unsigned int result[20];
unsigned int average;

void main(void)
{
  PCR = CLKDIV_3;                               // ICLK = SYSCLK / 3
  GCR = ZPLL_CLK_DIV_PRE_1;                     // SYSCLK = 8 x fOSC
  PCR |= PENABLE;                               // Enable peripherals

  REQMASK = 0;                            // clear interrupt mask
  REQMASK |= (1<<CIM_MIBADCE1);           // enable channel 27 (AD1)

  ADCR1 |= PS_8;                          // ADCLK prescaler = 8
  ADSAMPEV |= SEN;                        // ADCSAMP1 controls SW
  ADSAMP1 = 62;                           // SW = 62+2

  ADCR1 |= ADC_EN;                        // Enable ADC
  ADISR1 = 0x0001;                        // group 1 = channel 0

  ADEVTSRC = G1_SRC_INT1 + G1_EDG_SEL + G1_ENA; // enable group 1 and set trigger for low
                                                // to high transition
  ADBCR1 |= BUF_EN;                       // enable buffered mode
  ADBCR1 |= BNDA_8;                       // set RAM boundary between event and group 1
                                          // units of two words from the beginning of buffer
                                          // event group has 8*2 = 16 words for the FIFO
  ADBCR1 |= BNDB_16 + BNDB_2;             // set RAM boundary between group 1 and 2
                                          // units of two words from the beginning of buffer
                                          // group 1 has (18-8)*2 = 20 words for the FIFO
  ADBCR2 |= BNDEND_64;                    // set RAM buffer end boundary
                                          // 64-word FIFO buffer
                                          // group 2 has 64-(2*18) = 28 words for the FIFO

  ADTHRG1 = G1THR_16 + G1THR_4;           // group 1 threshold counter = 20, 20 results will be
                                          // placed on the buffer before setting G1 BUF INT FLAG

  ADBUFST &= ~G1_INT_FLAG;                // clear flag
  ADBCR3 |= G1_OVR_INT_EN;                // enable group 1 FIFO buffer over-run interrupt
  ADBCR3 |= G1_BUF_INT_EN;                // enable group 1 FIFO buffer interrupt

  HETGCR = CLK_MASTER + IGNORE_SUSPEND;   //  HET Master Mode, Ignore SW BP

  // Copy HET instructions to HET RAM
  MemCopy32((void *)&e_HETPROGRAM0_UN, (void *)HET_INIT0_PST,
            sizeof(HET_INIT0_PST));

  HETPFR  = 0x00000309;                   // Set LR Div = 8, HR Div = 10
  HETDCLR = 0xffffffff;                   // Clear HET output latches
  HETDIR = 0xffffffff;                    // Set HET as GIO outputs
  HETGCR |= ON;                           // Start HET

  __enable_interrupt();                   // enable interrupts

  while (1);                              // Loop forever...
}
//------------------------------------------------------------------------------
// This module programms the HET RAM with the HET code
//------------------------------------------------------------------------------
void MemCopy32(unsigned long *dst, unsigned long *src, int bytes)
{
  for (int i = 0; i < (bytes + 3) / 4; i++)
    *dst++ = *src++;
}
//------------------------------------------------------------------------------
// TMS470R1B1M Standard Interrupt Handler
//------------------------------------------------------------------------------

__irq __arm void irq_handler(void)
{
  switch ((0xff & IRQIVEC)-1)
  {
    case CIM_MIBADCE1  :                      // channel 27 (AD1) interrupt?
      if (ADBUFST & 0x0020)                     // buffer over-run?
      {
        ADISR1 = 0x0001;                      // clear buffer
        ADTHRG1 = G1THR_16 + G1THR_4;         // reset group 1 threshold
      }
      else
      {
        unsigned int i;
        ADBUFST &= ~G1_INT_FLAG;               // clear flag
        average = 0;
        for (i=0; i<20; i++)
        {
          result[i] = ADBUF1;                  // read FIFO value
          average = average + result[i];       // sum values
        }
        average = (unsigned int) average / 20;  // get average
        HETDOUT = average & 0xff;             // Output 8 LSBs to LEDs
      }
      break;
  }
}

 

  • Hi

    HET is a micro machine that runs independently of CPU once proper opcodes are loaded in the HET RAM and enabled.  From the above code snippet I could see that a HET RAM is loaded with opcodes, let us know what is programmed in the HET RAM ( either the het assembly code .het or the opcodes downloaded) to comment on your query.

    Which microcontroller are you using? let us know some more details of the ADC trigger source, which HET pin is used as trigger.

    Important Note : Please be aware that the TMS470R1x series is not recommended for new designs.Please see the full 'NRDN' notice here.

    Soon TI will be launching the new TMS470M series of microcontrollers. This series will feature greater ARM CPU performance and a similar peripherial set to the TMS470R1 Series of microcontrollers.  Please come back soon for more information about the TMS470M Series of microcontrollers.  The product preview for the first two microcontrollers in the TMS470M series is available here: TMS470MF0660x - SPNS157. The TMS470M Series Technical Reference Manual is available here: TMS470M TRM.

  • Thanks for your reply Prathap.

    Here is the code for HET RAM. I'm using TMS470r1b1m. Actually I'm not sure which HET pin is used to to trigger. Thanks again!

    HET_MEMORY const HET_INIT0_PST[1] =
    {

      // L00_0
     {
      0x00000601,
      0x00002000,
      0x00000000,
      0x00000000
     }
    };

    #define HET_L00_0 (e_HETPROGRAM0_UN.Program0_ST.L00_0)


    typedef union
    {
      HET_MEMORY Memory0_PST[1];
     struct
     {
      CNT_INSTRUCTION L00_0;
     } Program0_ST;

    } HETPROGRAM0_UN;

    extern volatile HETPROGRAM0_UN e_HETPROGRAM0_UN;

    extern const HET_MEMORY HET_INIT0_PST[1];

     

    Rui

  • Hi

    According to the Spec HET18 is the only trigger from HET module. The above mentioned HET code does not toggle or control HET18, it is a simple counter which can interrupt every 8192 LRP.

    But to really trigger RTI, HET18 should toggle( depends on the Event edge/type etc). Looking at the software you mentioned I do not see anywhere HET18 is toggled. Can you check if anything externally affects HET18 to trigger MIBADC.

    Best Regards
    Prathap

     

  • Thanks Prathap.

    It seems this code just use this simple counter to interrupt, as 11ms(90Hz) comes from. 59MHz/8192/80. The code mentioned above is all i have to run this algorithm. Could you tell me why the interrupt happens every 8192 LRP in the simple counter, Is there any preset value resulting this number '8192'? or is it just fixed? Can i find any information about this simple counter in the HET reference guide? It seems i didnt find those informations on the reference guide.

    Thanks a lot

    Rui  

  • The HET instruction used is CNT instruction with interrupt enabled. The count value is 8192, hence the CNT value gets decremented every one LRP. Hence after 8192 LRP it generates an interrupt.

    Please refer the instruction details in the HET reference guide.

    Best Regards
    Prathap

  • Hi Prathap

    Thanks for your reply and help, i will check it carefully.

    Rui