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TM4C1294NCPDT: TM4C1294NCPDT

Part Number: TM4C1294NCPDT


I m trying to generate the PWM channel 0.  I programmed the pll clock to be 100 Mhz. Then try to generate a pwm of frequency 100 KHz.  I am getting only 80 Khz.  The code below.  Could you help.

g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
                                             SYSCTL_OSC_MAIN |
                                             SYSCTL_USE_PLL |
                                             SYSCTL_CFG_VCO_480), 100000000);
void setupPWMClk(void)
{
    SysCtlPeripheralEnable(SYSCTL_PERIPH_PWM0);
    SysCtlPWMClockSet(SYSCTL_PWMDIV_1);
    SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
    GPIOPinConfigure(GPIO_PF0_M0PWM0);
       GPIOPinConfigure(GPIO_PF1_M0PWM1);
       GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_0);
          GPIOPinTypePWM(GPIO_PORTF_BASE, GPIO_PIN_1);
          GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_0, GPIO_STRENGTH_10MA, GPIO_PIN_TYPE_STD);
         PWMGenConfigure(PWM0_BASE, PWM_GEN_0, PWM_GEN_MODE_DOWN |
                             PWM_GEN_MODE_NO_SYNC);
          PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, 1000);
          PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0,500);
            PWMOutputState(PWM0_BASE, PWM_OUT_1_BIT | PWM_OUT_0_BIT, true);
  
             // Enables the counter for a PWM generator block.
             PWMGenEnable(PWM0_BASE, PWM_GEN_0);
}
  • Hello Ramesh,

    I would recommend you check the result of the MAP_SysCtlClockFreqSet function. See what value g_ui32SysClock is giving you back. The dividers will only divide down from the 480 MHz PLL, so I expect you will find the clock is set to 80 MHz which would then explain the 80 kHz PWM. If that is the case, you can tweak your PWM configuration to use 800 instead of 1000 and that should get you the 100 kHz output.
  • Hi Ralph,

    Actually I verified the system clock by toggling a gpio in Systick interrupt and it is 100 MHz. In the TM4c1294 userguide section 23.3.1 It is mentioned that system clock is used as input for pwm. Even if it derives from 480 MHz the output frequency should be more.

    I changed SysCtlPWMClockSet(SYSCTL_PWMDIV_1); to PWMClockSet(PWM0_BASE,PWM_SYSCLK_DIV_1); as per the Tiva library user guide. Even then the problem exists.

    Regards,
    Ramesh
  • Hello Ramesh,

    I am not sure what logic was put into the process of using a GPIO for measuring that, but I must insist on my prior stance. I ran your code and checked the result of ui32SysClock and it clearly is shown as 80 MHz.

    I then changed your code to adjust the PWM the generator and width set to:

        PWMGenPeriodSet(PWM0_BASE, PWM_GEN_0, 800);
        PWMPulseWidthSet(PWM0_BASE, PWM_OUT_0, 400);

    And with that I verified a 100 kHz PWM with 50% duty cycle is output on PF0.

    To avoid confusion, I would recommend clearly setting the frequency in SysCtlClockFreqSet to be what it will actually output, in other words use this call:

        ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ | SYSCTL_OSC_MAIN | SYSCTL_USE_PLL | SYSCTL_CFG_VCO_480), 80000000);

  • Hi Ralph,
    In your code you are setting to 80MHz as system clock. I am setting 100 Mhz since that is our requirement.

    g_ui32SysClock = MAP_SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
    SYSCTL_OSC_MAIN |
    SYSCTL_USE_PLL |
    SYSCTL_CFG_VCO_480), 100000000);

    To verify that the system is operating in 100 MHz, I programmed the systick as follows
    SysTickIntHandler(void)
    {
    //
    // Update the Systick interrupt counter.
    //
    g_ui32sysCounter++;

    char cOne, cTwo;


    psysTimerTick=true;

    if(toggle)
    {
    GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_7, GPIO_PIN_7);
    toggle=false;
    }
    else
    {
    GPIOPinWrite(GPIO_PORTL_BASE, GPIO_PIN_7, 0);
    toggle=true;
    }

    //
    // Update the interrupt status.
    //


    ROM_IntMasterEnable();
    }

    void
    initSystick(uint32_t ui32SysClock)
    {
    g_ui32sysCounter = 0;
    SysTickPeriodSet(ui32SysClock/10000); //1/100 MHz= .01 microsec and .01*10000=100 microsec
    psysTimerTick=false;

    toggle=false;
    }

    If I check PL7 I get a 5 Kz signal with 50% duty cycle.

    Regards,
    Ramesh
  • Hello Ramesh,

    The TM4C1294NCPDT will not run at 100 MHz. Period. It is not possible to configure it for that frequency as the internal PLL does not run at a multiple of 100.

    Either 120 MHz or 80 MHz are your options.

    Your measurement method is flawed and not providing the right results. The output of SysCtlClockFreqSet tells you the frequency accurately.

    I adjusted my code to say 80 MHz because that way others who program the device don't get the wrong idea of the system clock speed.
  • Hi Ralph,
    You are right. As you mentioned SysCtlClockFreqSet returns 80 MHz only. I was thinking the clock can be set anything upto 120 MHz. Could you point out this info in the user guide?


    Thank you very much for the support

    Regards,
    Ramesh
  • Hello Ramesh,

    The datasheet unfortunately does a poor job conveying such details, but the core explanation simply is that the PLL runs are either 320 MHz or 480 MHz based on system configuration and can only be divided down by integers to provide System Clock. Therefore, it is not possible to get 100 MHz as there is no integer that can divide 320 or 480 to be equal to 100. However, 80 MHz, 120 MHz, or 60 MHz are all possible settings.