• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 30 subscribers
  • Views 749 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TM4C1294NCPDT: Difference between TM4C1294NCPDT and TM4C129XNCZAD.

BocaDev
Intellectual 720 points
Part Number: TM4C1294NCPDT
Other Parts Discussed in Thread: TM4C129XNCZAD

Hello,

Can someone explain to me what the difference is between the TM4C1294NCPDT and the TM4C129XNCZAD device internal memory.

My compiler is complaining when I use a chip definition of TM4C1294NCPDT giving me "The downloaded program doesn't seem to match the expected memory layout of the target system"  within the debug log window.

When I select chip definition of TM4C129XNCZAD, no such errors.

My understanding is both devices have 1024K FLASH with 256K SRAM.

Thank you.

  • 0
    TI__Guru 72500 points
    They do have the same flash and RAM size. Can you give me some more information about the error message you received? Which tools are you using? Code Composer Studio? Which compiler and what version? If you capture an image of the error message using the Windows "Snipping Tool" you can save that image as a .png file. Then using the "Insert Code, Attach Files and more..." option, you can insert that image into your post.
  • 0 in reply to Bob Crosby
    Intellectual 720 points

    Hi Bob,

    Thanks for you reply.

    I am the person who reported this last month when using the IAR 8.32 Workbench. I have already reported this to IAR, but I realize it may take awhile for IAR to look into this issue. In the meantime, I thought I would continue looking into this to learn just what takes place when I click on the download and debug button.

    I  then discovered that by changing the defined processor from TM4C1294NCPDT to TM4C129XNCZAD, I no longer had these warnings. However some of the programs are not running as they had before. So that is where I am in my investigation, trying to figure out what is the difference between these two processors.

    This is a copy of the debug log I get when defining the processor as TM4C1294NCPDT. Within it you'll note the memory errors.

    Tue Dec 11, 2018 11:14:08: IAR Embedded Workbench 8.32.1 (C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\bin\armproc.dll) 
Tue Dec 11, 2018 11:14:08: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\debugger\TexasInstruments\TM4C129.dmac 
Tue Dec 11, 2018 11:14:08: Loading the I-jet/JTAGjet driver 
Tue Dec 11, 2018 11:14:08: Probe: Probe SW module ver 1.61 
Tue Dec 11, 2018 11:14:08: Probe: Option: trace(Auto,size_limit=100%) 
Tue Dec 11, 2018 11:14:08: Probe: Found I-jet, SN=72247 
Tue Dec 11, 2018 11:14:08: Probe: Opened connection to I-jet:72247 
Tue Dec 11, 2018 11:14:08: Probe: USB connection verified (10811 packets/sec) 
Tue Dec 11, 2018 11:14:08: Probe: I-jet, FW ver 7.2, HW Ver:A 
Tue Dec 11, 2018 11:14:08: Probe: None or IJET-MIPI10 adapter detected 
Tue Dec 11, 2018 11:14:08: Probe: Versions: JTAG=1.83 SWO=1.39 A2D=1.70 Stream=1.49 SigCom=2.44 
Tue Dec 11, 2018 11:14:08: Emulation layer version 4.38 
Tue Dec 11, 2018 11:14:09: SWD clock detected: 12MHz 
Tue Dec 11, 2018 11:14:09: Notification to init-after-power-up hookup. 
Tue Dec 11, 2018 11:14:09: Notification to core-connect hookup. 
Tue Dec 11, 2018 11:14:09: Connected DAP v1 on SWD. Detected IDCODE=0x2ba01477. 
Tue Dec 11, 2018 11:14:09: Connecting to TAP#0 DAP AHB-AP-CM port 0 (IDR=0x24770011). 
Tue Dec 11, 2018 11:14:09: Recognized CPUID=0x410fc241 Cortex-M4 r0p1 arch ARMv7-M 
Tue Dec 11, 2018 11:14:09: Debug resources: 6 instruction comparators, 4 data watchpoints. 
Tue Dec 11, 2018 11:14:09: MultiCore: Asynchronous core execution FORCED. 
Tue Dec 11, 2018 11:14:09: MultiCore: Synchronous core execution DISABLED. 
Tue Dec 11, 2018 11:14:09: LowLevelReset(system, delay 200) 
Tue Dec 11, 2018 11:14:09: CPU status - IN RESET 
Tue Dec 11, 2018 11:14:09: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.2\arm\config\flashloader\TexasInstruments\FlashTC4_256KB.out 
Tue Dec 11, 2018 11:14:09: Target reset 
Tue Dec 11, 2018 11:14:10: Downloaded J:\EK\TivaWare-2.1.4.178\examples\boards\ek-tm4c1294xl\blinky\ewarm\Exe\blinky.out to flash memory. 
Tue Dec 11, 2018 11:14:10: 1166 bytes downloaded into FLASH (0.74 Kbytes/sec) 
Tue Dec 11, 2018 11:14:10: Loaded debugee: J:\EK\TivaWare-2.1.4.178\examples\boards\ek-tm4c1294xl\blinky\ewarm\Exe\blinky.out 
Tue Dec 11, 2018 11:14:10: The downloaded program doesn't seem to match the expected memory layout of the target system: 
Tue Dec 11, 2018 11:14:10: Some SFRs are placed outside known memory areas, or in memory areas designated as read-only or as RAM: 
Tue Dec 11, 2018 11:14:10:   ROM_SCS @ 0xE00FF000, 32 bits 
Tue Dec 11, 2018 11:14:10:   ROM_DWT @ 0xE00FF004, 32 bits 
Tue Dec 11, 2018 11:14:10:   ROM_FPB @ 0xE00FF008, 32 bits 
Tue Dec 11, 2018 11:14:10:   ROM_ITM @ 0xE00FF00C, 32 bits 
Tue Dec 11, 2018 11:14:10:   ROM_TPIU @ 0xE00FF010, 32 bits 
Tue Dec 11, 2018 11:14:10:   and more... 
Tue Dec 11, 2018 11:14:10: Memory is specified as follows: 
Tue Dec 11, 2018 11:14:10:   0x00000000 - 0x000FFFFF  ROM/Flash 
Tue Dec 11, 2018 11:14:10:   0x01000000 - 0x1FFFFFFF  ROM/Flash 
Tue Dec 11, 2018 11:14:10:   0x20000000 - 0x2003FFFF  RAM 
Tue Dec 11, 2018 11:14:10:   0x22000000 - 0x227FFFFF  RAM 
Tue Dec 11, 2018 11:14:10:   0x40000000 - 0x400FFFFF  Uncached/SFR 
Tue Dec 11, 2018 11:14:10:   0x42000000 - 0x43FFFFFF  Uncached/SFR 
Tue Dec 11, 2018 11:14:10:   0x44030000 - 0x44030FFF  Uncached/SFR 
Tue Dec 11, 2018 11:14:10:   0xE0000000 - 0xE0002FFF  Uncached/SFR 
Tue Dec 11, 2018 11:14:10:   0xE000E000 - 0xE000EFFF  Uncached/SFR 
Tue Dec 11, 2018 11:14:10:   0xE0040000 - 0xE0041FFF  Uncached/SFR 
Tue Dec 11, 2018 11:14:10: SFRs range from 0x40000000 to 0xE00FFFFF 
Tue Dec 11, 2018 11:14:10: LowLevelReset(software, delay 200) 
Tue Dec 11, 2018 11:14:10: LowLevelReset(system, delay 200) 
Tue Dec 11, 2018 11:14:10: CPU status - IN RESET 
Tue Dec 11, 2018 11:14:10: 1166 bytes verified (284.67 Kbytes/sec) 
Tue Dec 11, 2018 11:14:10: Download completed and verification successful. 
Tue Dec 11, 2018 11:14:10: LowLevelReset(software, delay 200) 
Tue Dec 11, 2018 11:14:10: Target reset 
Tue Dec 11, 2018 11:14:10: INFO: Configuring trace using 'Auto,size_limit=100%' setting ... 
Tue Dec 11, 2018 11:14:10: Trace: Using detected ETMv3CM at address 0xe0041000 
Tue Dec 11, 2018 11:14:10: Trace: Access to detected ETMv3CM(architecture=3.5) initialized (CONF=0x8c842000, CTRL=0xc10, IDR=0x4114f250) 
Tue Dec 11, 2018 11:14:10: SWO: Manchester, Pin = TDO, Auto divider = 4 
Tue Dec 11, 2018 11:14:10: INFO: Cannot measure current when I-jet is not powering the target. 
Tue Dec 11, 2018 11:14:10: MultiCore: Synchronous core execution DISABLED. 
Tue Dec 11, 2018 11:14:10: There were 3 warnings during the initialization of the debugging session.

    Thanks,

    Alan

  • 0 in reply to BocaDev
    TI__Guru 72500 points
    The TM4C129XNCZAD has the 1-wire module at 0x400B6000 but the TM4C1294NCPDT does not. I have no idea if this relates to the warnings or issues you are having with the IAR tool.
  • 0 in reply to Bob Crosby
    Intellectual 720 points

    Thanks Bob,

    Seems that the IAR memory configuration file for the I-Jet debug probe is causing the problems when selecting the TMS4C1294NCPDT processor. I'll just use an older JTAG device until they come up with a corrected file.

    Thanks again Bob.

    Alan