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Original question:

TM4C1294KCPDT: VDDA Shorts VDD

VREFA shorts VDD

Genatco
Guru 56033 points
Part Number: TM4C1294KCPDT
Other Parts Discussed in Thread: REF2033

Perhaps VDD, VREFA, VDDA short occurred after powering analog comparator C0+ VREF pin PC6 via REF2033, causation 500us power up delay. What exactly are consequences to MCU from powering PC6 of analog comparator with 500us delay? Obviously when analog comparator PC6 is powered directly from 3v3 rail no shorts occur on VDD, VERFA, VDDA. Again the internal reference was software selected, VREFP configured VDDA. Note too EKXL-EVM, VREFA+ is also powered 3v3 rail via R41 without recommended parallel caps, (1uf/100nf).  

Is latter delay (500us) considered powering ADC from a separate power supply? Can delay powering external threshold PC6 somehow causes excessive current to flow from VDD (3v3 rail) into VDDA of analog comparator without PC6 being shorted in the process? Would it not behoove the community to know it is considered safe practice to delay powering PC6 as MCU is in progress of being or has been fully powered several hundred microseconds before PC6? 

Please confirm latter configuration conditions can not or will not stress VDDA or VREFA in the process of powering VDD too. How many engineers have ever reported this forum may lead to shorting of VDD,VDDA,VREFA after PC6 being delayed powering 500us? It would seem typical practice powering c0+ (PIN0) via potentiometer tied directly to VDD 3v3 rail. What is the solution to safely use REF2033 with PC6 threshold input directly or via potentiometer divider?

Should we not initially configure PC6 to later compensate >500us delay after POR as safe work around to use REF2033 as described?

  • 0
    TI__Guru 72500 points
    I don't think the delay of 500uS is a problem on power up. The delay means that PC6 does not see any voltage higher than VDDA. You might want to look at the power down sequence. Also, did the problem happen while controlling a motor? Motors are notorious for inductive voltage kickbacks that either directly, or indirectly through magnetic coupling, can create voltages that will induce an electrical overstress.
  • 0 in reply to Bob Crosby
    Guru 56033 points

    Hi Bob,

    It is a complete mystery that occurred only after REF2033 was wired to power RV1 into PC6. One time I simply touched DMM +probe on RV1 TP15, first grounding both probe tips. The first MCU required DNP C71 near PC6 input. The 3rd MCU required C71 or easily tripped threshold (2.54v) as VREFA noise level increased. Now 3 Cn- inputs are configured, output OD and trip randomly as expected.

    Oddly the 1st MCU at one point required removal C71 or tripped phantoms under heavy loads. Had configured only two Cn- inputs. Not sure why 1st MCU disliked three Cn- inputs, other than TW may have damaged not being OD coupled to 3 PWM fault inputs. Perhaps TW damaged 1st MCU as 2nd/3rd MCU CnO are configured OD, WPU on Mfault inputs works well.

  • 0 in reply to Bob Crosby
    Guru 56033 points
    Hi Bob,

    Perhaps VREFA+ being powered concurrently with VDD yet well before PC6 much slower rising potential (REF2033) causes excessive internal current flow from VREFA+ >40µA stressing VDDA/VDD rail of the analog comparator? Logical deduction being analog port PC6 is push pull current limited by the default pin type 2-8mA?

    There is no current limiting on our VREFA+ input via (R150/0R) or EVM (R41/0R). Past adding >R to limit current caused >40µA current to flow across JP2 of EVM. If 40µA is maximum VREFA+ how can current other wise rise across JP2 testing pins? That VREFA+ exceeding >40µA seems the likely place as any to cause VDDA damage does it not? After all VREFA+ then measures 12 ohms to GNDA and VDD 1.3 via post mortem analysis.