Hi,
With the TMS570LC, we implemented a debugger script that was automatically sending / receiving SPI commands (we are not in MibSPI mode). That script is a copy of embedded C code that works: the script performs the exact same register reads/writes. However, the script does not work:
- We are sending a command to an external FPGA by sending an SPI frame (i.e. writing to SPIDAT1)
- Since we do not expect useful answer, we want to discard the received frame. For that, we read SPIBUF register to pop the received frame from the RXBUF or SPIBUF. We loop on that operation until no more message is found in the RX FIFO (i.e. until SPIBUF[RXEMPTY]=1). However, that bit is never set to 1.
In C code, it is set to 1 after a single read. Through the debugger, it always remains zero, which indicates there is still data to be popped. Hence, we are inferring that there is a non-documented feature in the MibSPI module where it gets the ID of the master that is making transactions through the Peripheral Interconnect. If the transaction comes from the JTAG DAP/DMM/RTP debug module, then the MibSPI module behaves differently and returns the content of the SPIBUF, but without allowing reads to alter the state of the module. If it comes from another master, it behaves as documented.
That would be logical since in their GUIs, debuggers show the value of registers. If showing that would pop messages, the debugger's presence would corrupt the behavior. Still, it would have been nice that this feature be documented as we wouldn't then had tried to do SPI transmissions / receptions through the debugger. Can you confirm hidden behavior?
Thanks.
Étienne
