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TM4C1294KCPDT: ADC SNR PHY TXD

Genatco
Guru 55913 points
Part Number: TM4C1294KCPDT

Issue EMAC0 PHY stops TXD'ing when AINx EMF noise increased SNR via near MCU pin mounted decoupling caps. Good thing was RXD then accepted one last command - STOP after TXD crashed!

It would seem ADC0 SNR subjects PHY/USB0 to sudden death and RXD remained responsive until LWIP routing error occurs. MCU pin decoupling caps (200pf) should lower RS impedance (AINx) but encouraged attacks upon TXD/USB0 computer end points. Lowering decoupling cap value (100-51pf) stopped PHY TXD port crashing from typical and expected ADC0 SNR. USB0 endpoint has fewer crashes 30mhz clock than 60mhz, even after PHY remains connected after reducing AINx SNR.

Suspecting ADC0 SNR being a bit high bleeds into other peripherals, perhaps via AHB? Oddly several EVM tested never presented this issue via X11 header, multilayer PCB somehow reduces ADC0 SNR? Also reducing (EN0Rx/Tx-N/P) 1000n caps to 39n near MCU pins did produce some improvement, 100n did not. Oddly the PHY Bob filter caps where first reduced from 4.7uf to 0.22uf did not stop TXD from crashing.  

 

  • 0
    TI__Guru 72500 points
    If the signals on the ADC input pins exceed Vccad or go below ground they will affect the levels on other pins. The difference between the two sided boards and the multi-layer board is probably the ground plane. A ground plane very effectively reduces the size of the unintentional loop antenna created by signal traces. If there are large, fast switching currents nearby, the magnetic field will be picked up in the loop antenna and create a noise voltage on that signal.
  • 0 in reply to Bob Crosby
    Guru 55913 points

    Bob Crosby said:
    If the signals on the ADC input pins exceed Vccad or go below ground they will affect the levels on other pins

    Perhaps you missed  200pf were ANIx decoupling capacitors tied to AGND plane under MCU bottom side layer. It seems AGND transients input to ANix rather than exit to AGND. Reducing ANIx decoupling capacitance also sits parallel CADC (10pf) may increase CADC 210pf? The same AINx transients are present in either capacitance value. Yet lower cap values obviously reduce internal SNR and higher capacitance values seem to increase SNR noise levels input from AGND. 

    Oddly ADC1 CH16 SNR still increases during EMF even with resistive value to AGND replaced any decoupling capacitance. There is no explanation why channel 16 FIFO values increase on every MCU we tested as no SNR source exists on either side MCU pin 18 other than DGND pin 17.  It seems there is internal high impedance between MCU package pin 18 to DGND pin 17, Seemingly explains why other SNR mayhem is occurring relative to AINx pins!

    Bob Crosby said:
    A ground plane very effectively reduces the size of the unintentional loop antenna created by signal traces

    It would seem there is destructive threshold ANIx capacitance when quieter DGND has been separated from noisy AGND input sources of GPIO configurations. The datasheet assumes one ground plane, in both cases SNR when considering RS impedance (Tina DC analysis) lowers via larger values of AINx capacitance. Even though MCU GNDA pin is tied to DGND trace any decoupling capacitance added to ANIx raises ADC0 specified SNR and AGND transients invade RS impedance in a bad way that also effect both PHY.