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TMS570LC4357: Interfacing on EMIF with asynchronous 2x8bit MRAM (MR4A08BUYS45)

Part Number: TMS570LC4357

Dear TI support,

we are willing to interface MRAM components from Everspin on the EMIF interface of the TMS570LC4357. Two options are considered:

Option 1: 2x 8bit MR4A08BUYS45 operated on the 16bit EMIF and providing 4MB of MRAM in total

Option 2: 1x 16bit MR4A16BUYS45 operated on the 16bit EMIF and providing only 2MB of MRAM per Chip Select channel (i.e., 3x2MB in total)

The implementation of Option 2 is easy since the MR4A16BUYS45 provides directly pins that can be connected to the nCS, nOE, nWE, nDQM pins of the TMS570LC4357.

The implementation of Option 1 is unclear, but it would provide a higher amount of memory to the application. In fact, the 8bit version of the MR4A08BUYS45 does not provide any pins specifically able to be connected to the nDQM pins of the TMS570LC4357. The addresses of both MR4A08BUYS45 to form a 16bit data interface would be connected together, starting from EMIF_BA[1] (connected to A00) up to EMIF_ADDR[19] (connected to A20). The nWE would be connected to nW, the nOE to nG, and the nCS to the nE. But what about the nDQM[0] and nDQM[1]? Can the TMS570LC4357 drive 2x MR4A08BUYS45 connected on the same nCS[2] and using them as they would be one single 16bit memory?

One idea for the implementation of Option 1 could be to use the nDQM[0] and nDQM[1] as Chip Select signals (and instead of the nCS[4:2] of the TMS570) and connect them to the respective nE pins of the MR4A08BUYS45. In this case, probably the Select Strobe Mode described in the SPUN563A starting from page 818 would do the job since the nDQM are valid before the nOE and nWE strobes. Unfortunately, not using the nCS signals would make the design useless, since we also have SDRAM installed on the EMIF.

Has somebody an advice to this idea and how it could work well?

Note that adding a logic function between signals (e.g. OR gate between nCS and nDQM) is not an option for this design.

Datasheet of both 8bit MR4A08BUYS45 and 16bit MR4A16BUYS45 is available under the following link: www.everspin.com/.../MR4A08BUYS45

Best regards

Vincent

  • This is being looked at. Feedback will be delayed due to holidays.
  • Hello Vincent,

    The better way is to use OR gate (CS, and DQM signals). If OR gate is not an option, please use 1 CS only for both devices. 1 device connects to EMIF D[7:0]; the other connects to EMIF D[15:8].
  • Thank you QJ.

    Indeed, using external OR gates is not an option in this design, but I am wondering if it could be simply done by defining that all the data READ (this is actually the case since the EMIF_nDQM are always active during READ commands) and WRITE commands must be performed on 16bit strictly. This could be defined as rule in all READ and WRITE accesses to the MRAM. In this configuration, we would exactly use the connection you proposed. Could you confirm that it can be defined in this way, that all the WRITE accesses are always on 16bit and no masking through nDQM signals is used (EMIF_nDQM[1:0] would not be connected and used in the MRAM memories)?

    Best regards

    Vincent

  • Hi Vincent,

    Yes, you can use this way.

    Since the nDQM[1:0] are not used, you can not use 8-bit pointer. 16-bit and 32-bit pointers should be fine. Let's say you want to write to the first word and 2nd word of the async RAM you can use below code as an example.

    *(uint16 *)0x60000000 = 0x1234; // Write 16-bit value 0x1234 to the first location.
    *(uint16 *)0x60000002 = 0x5678; // Write 16-bit value 0x5678 to the 2nd location.
  • Hi QJ Wang,

    thank you very much: this confirms my expectation and solves the questions.

    Best regards

    Vincent