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RM46L852: N2HET as GIO interrupts

Marc Hewitt
Prodigy 180 points
Part Number: RM46L852

Hello all,

I have a quick question.

I have configured N2HET2 bits 4, 6 and 8 as GIO.

Then I went to edge interrupts and enabled edge0, edge1 and edge2 and told them to interact with HET2 4, 6, 8 bits on rising edge only.

Then I went to PIN 0-7 and configured bits 4 and 6 as input with pull up.

Lastly I got PIN 7 - 15 and configured bit 8 as input with pull up (same as previous ones).

On HET2 I placed three buttons.

On GIOB I have three LEDs.


I would like to turn on each LED by the push on the button via interrupt (notification.c).

When I turn them via sys_main.c all works fine.


How would I do that?
What do I need to turn on in VIM?


Trying to enable HET High / HET Low just produces the error.

I thought they might go to gioNotification and enabled GIO interrupt, but that doesn't seem to be the case.

So, I believe they will interact in edgeNotification, hence I've done this:

gioInit ();
hetInit ();

gioSetDirection (hetPORT2, 0x00000000);

gioEnableNotification (hetPORT2, 4U); // thought this would help but didn't
edgeEnableNotification (hetREG2, 0U);
_enable_IRQ ();

Can you tell me what I am doing wrong? :)

Thanks and Happy New Year!

Marc

  • 0
    TI__Guru**** 161600 points
    This is being looked at. Feedback will be delayed due to holidays.
  • 0 in reply to Yordan Kovachev
    TI__Guru**** 197036 points
    Hello Marc,

    1. Please enable NHET2 interrupt in VIM (channel 63 and channel 73). The NHET ISR will be generated in het.c: het2HighLevelInterrupt(void) and het2LowLevelInterrupt(void). Those 2 ISRs call edgeNotification()
    2. You can add the code to turn on/off LED in edgeNotification()

    In the N2HET interrupt service routine, the main CPU must first determine which source inside the N2HET created the interrupt request. This operation is accelerated by the N2HET Offset Index Priority Level 1 Register (HETOFF1) or N2HET Offset Index Priority Level 2 Register (HETOFF2) that automatically provides the number of the highest priority source within each priority level. Reading the offset register will automatically clear the corresponding N2HET interrupt flag that created the request. However, if the offset registers are not used by the N2HET interrupt service routine, the flag should be cleared explicitly by the CPU once the interrupt has been serviced.

    For your case, the interrupt sources are instruction 17, 18, and 19 (het.c):
    },
    /* ECNT: CCU Edge 0
    * - Instruction = 17
    * - Next instruction = 18
    * - Conditional next instruction = 18
    * - Interrupt = 17
    * - Pin = 4
    */
    {
    /* Program */
    0x00025440U,
    /* Control */
    (0x00024007U | (uint32)((uint32)4U << 8U) | (uint32)((uint32)2U << 4U)),
    /* Data */
    0x00000000U,
    /* Reserved */
    0x00000000U
    },
    /* ECNT: CCU Edge 1
    * - Instruction = 18
    * - Next instruction = 19
    * - Conditional next instruction = 19
    * - Interrupt = 18
    * - Pin = 6
    */
    {
    /* Program */
    0x00027440U,
    /* Control */
    (0x00026007U | (uint32)((uint32)6U << 8U) | (uint32)((uint32)2U << 4U)),
    /* Data */
    0x00000000U,
    /* Reserved */
    0x00000000U
    },
    /* ECNT: CCU Edge 2
    * - Instruction = 19
    * - Next instruction = 20
    * - Conditional next instruction = 20
    * - Interrupt = 19
    * - Pin = 8
    */
    {
    /* Program */
    0x00029440U,
    /* Control */
    (0x00028007U | (uint32)((uint32)8U << 8U) | (uint32)((uint32)2U << 4U)),
    /* Data */
    0x00000000U,
    /* Reserved */
    0x00000000U
    },
  • 0 in reply to QJ Wang
    Prodigy 180 points
    QJ Wang,

    Thank you for your reply! :)

    I completely understood what I've been missing. :)

    Just one quick additional question.
    Am I blind or are there no interrupts: HET1 Level 0 and Level1?
  • 0 in reply to Marc Hewitt
    TI__Guru**** 197036 points
    Hi Marc,

    There are NHET level 0 and level 1 interrupts. They are located at VIM channel 10 and channel 24.