TMS570LC4357: CPU reset during LBIST

user5896989

Part Number: TMS570LC4357

Hello,

I have some questions about CPU reset during LBIST

In TMS570 Technical Reference Manual (chapter 10.9.1 Example: STC1 Self-Test Run)

--> If BOTH Cores are configured in parrallel during the STC1 Segment0 seltest (SEG0_CORE_SEL = 0x0), there's only 1 or 2 CPU reset at the end of the selftest?
--> in case of CPU reset what's happen : all TMS is reseted or only internal ARM core?
--> If only ARM core is reseted, Software in FPROM starts in address 0x0 after the CPU(s) reset?

In chapter 10.10 (Self-Test Controller Diagnostics)

--> For steps2 or 3 or 4 or 5 is there a CPU reset after the completion of each Selftest?

over 6 years ago

0 Miro over 6 years ago

TI__Mastermind 21425 points

Hello,
At the end of the self test, STC generates CPU reset (not system reset). The CPU will restart execution from the reset vector - 0x00000000.

Best regards,
Miro

0 user5896989 over 6 years ago in reply to Miro

Prodigy 220 points

Hello,

The second part of my question concerns the Seltest Controller Diagnostics and the following procedure (Chapter 10.10 of technical Reference Manual):

"Step 1: Configure the interval count to 1 in STCGCR0 register.

Segment 0
Step 2: Enable the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register and kick off the
self-test by enabling the first interval of segment 0. On the completion of self-test, TEST_FAIL bit will be
set in the STCGSTAT register. Check if the FSEGID bits in the STCFSTAT register are set to 00.
Depending on the segment 0 configuration (parallel or individual cores), the CORE1_FAIL or
CORE2_FAIL bits would be set.
Step 3: Disable one or both of the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register.
Then restart the self-test by programming bit 0 of the STCGCR0 register to 1. On the completion of the
test, the TEST_FAIL bit will be cleared in the STCGSTAT register.

Segment 1 (for STC1 only)
Step 4: Configure the SEGID_PLOAD bits in STCSEGPLR register to select the first interval of segment 1.
Configure RS_CNT bit in STCGCR0 register to 1. This will start the self-test from the first interval of the
selected segment. On the completion of self-test, TEST_FAIL bit will be set in the STCGSTAT register.
Check if the FSEGID bits in the STCFSTAT register are set to 01.
Step 5: Disable one or both of the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register.
Then restart the self-test by programming bit 0 of the STCGCR register to 1. On the completion of the test,
the TEST_FAIL bit will be cleared in the STCGSTAT register."

--> It isn't mentioned there's a CPU Reset in Step2 or Step4 . Is there a CPU Reset or not ?

Best regards,

François