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TMS570LS3137: Work-around for EMIF async-memory causes extra WE pulse

jimj2713
Expert 2375 points
Part Number: TMS570LS3137

I have the issue explained in the Errata, where the EMIF-asynchronous-memory configuration causes extra WE pulses. The interesting thing is I have 2 identical external devices connection to EMIF_CS2 and EMIF_CS4, and the CS2 peripheral works on all of my boards and the CS4 peripheral works on none of them.

I saw the Errata work-around, which indicated to configure the MPU-region as strongly-ordered or device-type. I had already been using the strongly-ordered type (which works for CS 2 and not for CS4). I tried both shareable and non-shareable device-types, and CS4 still does not work.

2 questions:

1. Is the work-around supposed to be shareable or non-shareable, or do you think it matters?

2. Is it worth me trying the CS3 peripheral, and do you think (like my current CS2/CS4 experience) that it will either work on ALL boards or not work on ALL boards?

Thanks,

Jim

  • 0
    Expert 2375 points
    A little more information -- I moved the CS4 peripheral to the CS3 memory space (and changed the chip-select), and I changed the MPU to non-shared/device-type, and it appears to work on the one board I have. So the next question is, can I trust that future boards will also work?
    Thanks,
    Jim
  • 0 in reply to jimj2713
    TI__Guru**** 196776 points
    Jim,

    The workaround is to configure the async memory as "device" or "strongly-ordered". It doesn't matter to be "shareable or non-shareable". It should work for both nCS3 and nCS4.

    The start address of nCS4 region is 0x6800_0000. Please probe the nCS4 signal to make sure there is no signal routing issue (ball M17).
  • 0 in reply to QJ Wang
    Expert 2375 points

    QJ,

    Thanks for the quick reply. The CS4-problem was exactly as the errata described, so I am confident in the board layout. I have gotten this to work by moving to the CS3 region. My only concern now is whether I can count on both the CS2 and CS3 regions working without the errata problem on my future boards. We are buying expensive EP parts, so there is concern here about whether we can count on this CS2 and CS3 solution on future (very expensive) boards.

    I know you cannot give me a guarantee, but if you could give me your opinion about these 2 questions, it would be appreciated:

    1. Do you think this behavior would be consistent on different CPUs -- if they are from the same die-revision?

    2. Has this die been consistent for a long time -- so that I would expect all of my CPUs are from the same dies? There is a die-identification register; do you think I should get the same value from all CPUs I have? I know it is possible to get old parts from a distributor; I am just asking if it is likely all of my CPUs are some recent die-rev?

    Thanks,

    Jim

  • 0 in reply to jimj2713
    TI__Guru**** 196776 points

    Hi Jim,

    I don't know why the workaround doesn't work for nCS4 in your test. The only difference between CS3 and CS4 is the starting address of the memory region and their MPU settings. I will do a test using LS3137ZWT device.The performance or behavior should be the same for all the devices with same rev silicon.

    You can check the silicon revision number either from the Device ID code register or from the revision number from the symbols marked on the top of the device.

    ID register:

    • Rev A = 0x802AAD05

    • Rev B = 0x802AAD15

    • Rev C = 0x802AAD1D

    • Rev D = 0x802AAD25

    Symbol:

    3137DZWTxxx or 3137CZWTxxx