TMS570LC4357: CPU interconnect and ECC error injection

Sorry there was editing issue in the previous post :

I noticed in this related post , e2e.ti.com/.../628779, that the interconnect was able to generate and evaluate ECC.

Therefore I would like to know if there was a possibility (for example via a internal diagnotic or the SCm registers ) to insert an ECC error between the EMIF (or L2RAM) for example and the interconnect, for test purpose.

Thanks,

Regards,

Hello,

The EMIF doesn't support ECC checking on any external device. The interface to the EMIF supports ECC checking on the transactions to/from the EMIF. There is no mechanism to self test this EMIF ECC value.

Alright,

I suppose i know the answer but there is there a way to inject an ECC error between a transaction from the interconnect to the L2RAM ?

Thanks

Regards

Hello,

There is no mechanism to inject ECC error between the interconnect and the L2 RAM.

Then, how can we test that the ECC evaluation logic in the L2RAM, Flash or EMIF Bridge still works?

Suppose after a couple of hours of operation the ECC evaluation logic of the EMIF Bridge fails and always gives a PASS result for ECC. That fault will cause no immediate harm - it will be dormant.
Then, after more operating hours, the ECC generation logic in the core fails and starts to generate wrong ECC codes. Upon the next write to EMIF space, the EMIF Bridge will not detect that the core's transaction has a bad ECC and the transaction will reach the EMIF module. Wrong behavior will then occur.

So we need to way to make sure the ECC checker in the slaves is still alive. Any thoughts?

Thanks,
Étienne

Any answer?