Tool/software: Code Composer Studio
Hello. I'm working on a project right now.
I am currently working on a project to test the TCAN4550-Q1 using the TMS570LC4X.
One of the two boards is TX and the other board is RX. One of them is TX CODE and the other is RX.
But there's a problem here, and I'm going to contact you.
I'll talk about this.
Receiving a signal at rx when it is continuously transmitting at tx, the signal at tx stops, and rx receives the signal and transmits it to spi, confirming that it enters the corresponding rx buffer. No, the signal does not go in at once. I have to do it several times. When receiving the rx signal from the tx signal, it is necessary to send the recognized signal by confirming that rx has been received.
What I did when I sent the signal on rx basis.
Please review once.
I wonder if I need to take another action to get the rx signal.
I want to know how the signal is constant.
I will put the contents and the pictures I have together.
Please teach me a lot.
Register | Address | Action | Value | NOTES |
Device Interrupts |
0x0820 | READ | 0x80000082 | M_CAN_INT bit is set, so MCAN has an interrupt |
IR | 0x1050 | READ | 0x00000010 | New message in RX FIFO 1, need to read RX FIFO 1 status to get more information |
IR | 0x1050 | WRITE | 0x00000010 | Clear the interrupt by writing the bit back to the IR register |
RXF0S | 0x10A4 | READ | 0x00040301 | There is 1 unread message in the FIFO at index 3 |
- | 0X81C8 | - | - | Based on setup in Table 7, start address for index 3 is: hex(72 * 3) +0x80F0 = 0x81C8 |
RX FIFO0[3] | 0x81C8 | READ | 0x52345678 | Header word #1, XTD is set and ID[28:0] = 0x12345678 |
RX FIFO0[3] | 0x81CC | READ | 0x01B70000 | Header word #2, 7 bytes of data sent with CAN FD and BRS enabled |
RX FIFO0[3] | 0x81D0 | READ | 0x44332211 | First 4 bytes of data, 0x11 is the first received byte |
RX FIFO0[3] | 0X81D4 | READ | 0x00776655 | Last 3 bytes of data, 0x77 was the last received byte |
RXF0A | 0X10B8 | WRITE | 0x00000003 | Write the index of the FIFO index read to acknowledge that it has been read and clear it for use |
* read write spi