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CCS/TMS570LC4357: Why the RXERRCODE is 2h?

Part Number: TMS570LC4357
Other Parts Discussed in Thread: TMS570LS3137, , HALCOGEN

Tool/software: Code Composer Studio

While I am using the Emac module,I found that I can't transmit message to PC or receive from it.

And I read the valuer of 2h from the register named RXERRCODE(MACSTATUS).

But the same code can work with TMS570LS3137.

Is there something wrong in my seeting?Here is the code file:

static void TMS570EmacTXData(void)
{
static EMACDesc_t* const SL_FirstTXDescPtr = EMAC_RAM_BASE(#define EMAC_RAM_BASE           ((EMACDesc_t*)(0xFC520000UL))     /*CPPI RAM*/) + ARRAY_SIZE(EMAC_SL_HWRXBuffer); /*第一帧发送HDP所在位置*/
EMACDesc_t* DescPtr = SL_FirstTXDescPtr; /*当前发送数据的HDP*/
uint8_t Owner = 0u; /*CPU是否已经取得所有DESC的控制权*/
uint8_t EOQ = 0u; /*EMAC硬件模块是否已经处理完上一个DESC队列*/

/*1============================================================================1*/
/*判断发送缓冲区中的数据是否已经全部发送完毕*/
while ( DescPtr != NULL )
{
Owner |= DescPtr->OWNER;//=0
if ( DescPtr->NextPtr == NULL )//第一次过
{
EOQ = DescPtr->EOQ;//=0
}
DescPtr = DescPtr->NextPtr;//=0,eoq=0,onxer=1
}
/*1============================================================================1*/

/*1============================================================================1*/
/*EMAC硬件发送模块中的数据已经发送完毕,可以再次发送新的数据。*/
if ( (((EMAC_TXINTSTATRAW & 1u) == 1u) && (EOQ == 1u) && (Owner == 0u) && (EMAC_TX0HDP == 0u)) //第三次由第一个条件过
|| (SL_FirstTXDescPtr->BufferPtr == NULL) )
{
DescPtr = SL_FirstTXDescPtr;

while ( EMAC_SL_TXBuffer.Head.Cnt != EMAC_SL_TXBuffer.Tail.Cnt )//第一次没过,后面过了
{
/*2============================================================================2*/
/*配置发送缓冲区寄存器*/
memset(DescPtr, 0U, sizeof(EMACDesc_t));
DescPtr->BufferPtr = EMAC_SL_TXBuffer.Data[EMAC_SL_TXBuffer.Head.Cnt].Buffer; /*存放待发送数据的缓冲区*/
DescPtr->NextPtr = DescPtr + 1U; /*下一帧发送缓冲区*/
DescPtr->Length = EMAC_SL_TXBuffer.Data[EMAC_SL_TXBuffer.Head.Cnt].Len; /*数据长度*/
DescPtr->PacketLen = EMAC_SL_TXBuffer.Data[EMAC_SL_TXBuffer.Head.Cnt].Len; /*数据长度*/
DescPtr->SOP = 1U; /*起始标志位*/
DescPtr->EOP = 1U; /*结束标志位*/
DescPtr->OWNER = 1U; /*标志本数据控制权交由EMAC模块*/
/*2============================================================================2*/

/*2============================================================================2*/
/*更新发送队列信息*/
EMAC_SL_TXBuffer.Data[EMAC_SL_TXBuffer.Head.Cnt].Len = 0U;
EMAC_SL_TXBuffer.Head.Cnt++;
/*2============================================================================2*/

DescPtr++; /*指向下一个发送缓冲区*///fc5201b0
}/*优先发送ARP或者通信协议数据*/

while ( (EMAC_SL_IsGotRemoteMacAddr) && (EMAC_SL_IsRXRemoteUDPData)
&& (EMAC_SL_StandardOuputMSG.Head.Cnt != EMAC_SL_StandardOuputMSG.Tail.Cnt) )
{
EMACTXData_t* EMACDataPtr = EMAC_SL_StandardOuputMSG.Data + EMAC_SL_StandardOuputMSG.Head.Cnt; /*当前存放数据的缓冲区*/
MACFrame_t* MacFramePtr = (MACFrame_t*)(EMACDataPtr->Buffer);
IPHeader_t* IPHeaderPtr = (IPHeader_t*)(EMACDataPtr->Buffer + 14U);
UDPHeader_t* UDPHeaderPtr = (UDPHeader_t*)(EMACDataPtr->Buffer + 34U);
uint16_t PacketLen = MAX(MIN_IP_DATA_LEN, EMACDataPtr->Len);

memcpy(MacFramePtr->DstMacAddr, EMAC_SL_RemoteMacAddr, sizeof EMAC_SL_RemoteMacAddr); /*目的网卡MAC地址*/
IPHeaderPtr->TotalLen = EMACDataPtr->Len - 14U;
IPHeaderPtr->Identification = EMAC_SL_IPFrameID++;
TMS570EmacFillIPHeaderCheckSum((uint8_t*)(IPHeaderPtr));
UDPHeaderPtr->DataLen = EMACDataPtr->Len - 34U;
UDPHeaderPtr->CheckSum = TMS570EmacCalcUDPCheckSum(REMOTE_MSG_PORT,
EMACDataPtr->Buffer + UDP_HEADER_LEN, EMACDataPtr->Len - UDP_HEADER_LEN);

/*2============================================================================2*/
/*配置发送缓冲区寄存器*/
memset(DescPtr, 0U, sizeof(EMACDesc_t));
DescPtr->BufferPtr = EMACDataPtr->Buffer; /*存放待发送数据的缓冲区*/
DescPtr->NextPtr = DescPtr + 1U; /*下一帧发送缓冲区*/
DescPtr->Length = PacketLen; /*数据长度*/
DescPtr->PacketLen = PacketLen; /*数据长度*/
DescPtr->SOP = 1U; /*起始标志位*/
DescPtr->EOP = 1U; /*结束标志位*/
DescPtr->OWNER = 1U; /*标志本数据控制权交由EMAC模块*/
/*2============================================================================2*/

/*2============================================================================2*/
/*更新发送队列信息*/
EMAC_SL_StandardOuputMSG.Data[EMAC_SL_StandardOuputMSG.Head.Cnt].Len = UDP_HEADER_LEN;
EMAC_SL_StandardOuputMSG.Head.Cnt++;
/*2============================================================================2*/

DescPtr++; /*指向下一个发送缓冲区*/
}/*发送软件运行输出信息(为了保证能够完整地接收到所有的输出信息,只有建立网络连接后再尝试发送)*/

if ( DescPtr != SL_FirstTXDescPtr )//mmeiguo,第二次过了
{
DescPtr--;
DescPtr->NextPtr = NULL; /*将最后一个发送缓冲区的NextPtr置为空,表示发送到此缓冲区便结束*/
EMAC_TX0CP = EMAC_TX0CP;
EMAC_TX0HDP = (uint32_t)(SL_FirstTXDescPtr); /*开始发送数据(本语句必须放在最后)*/
}
}
/*1============================================================================1*/
}

typedef struct EMACDescStr {

struct EMACDescStr* NextPtr; /*下一个数据信息的指针*/
uint8_t* BufferPtr; /*存储数据的缓冲区地址*/
uint16_t Offset; /*数据存储缓冲区中第一个有效字节所在的位置*/
uint16_t Length; /*数据存储缓冲区中有效数据的长度,单位为字节*/
uint_t SOP : 1; /*数据帧第一个数据包标志位*/
uint_t EOP : 1; /*数据帧最后一个数据包标志位*/
uint_t OWNER : 1; /*数据帧当前的控制权是否属于CPU标志位*/
uint_t EOQ : 1; /*数据包是否为数据帧中的最后一包标志位*/
uint_t TDOWNCMPLT : 1; /*Teardown Complete (TDOWNCMPLT) Flag*/
uint_t PASSCRC : 1; /*数据包的CRC是否由EMAC模块生成标志位*/
uint_t JABBER : 1; /*Jabber frames are frames that exceed the RXMAXLEN in length, and have CRC, code, or alignment errors*/
uint_t OVERSIZE : 1; /*数据包数据长度过大报警*/
uint_t FRAGMENT : 1; /*数据包不完整报警*/
uint_t UNDERSIZED : 1; /*数据包数据长度过小报警*/
uint_t CONTROL : 1; /*本帧数据为控制帧数据*/
uint_t OVERRUN : 1; /*数据包接收覆盖报警*/
uint_t CODEERROR : 1; /*数据包内容错误报警*/
uint_t ALIGNERROR : 1; /*数据包对齐错误报警*/
uint_t CRCERROR : 1; /*数据包CRC错误*/
uint_t NOMATCH : 1; /*数据包MAC地址不匹配报警*/
uint16_t PacketLen; /*整帧数据的长度*/
}EMACDesc_t;

  • Hello,

    1. Please check your pinmux settings. TMS570LC4357 has alternative terminals for Ethernet pins.
    2. Can you try the test with the cache disabled?
    3. What is the clock for the emac in your case?
  • I'm so sorry that  the phenomenon has changed , the MACSTATUS register is always 00500000 while reading.

    1.I checked the pinmux file:

    void muxInit(void){

    /* Enable Pin Muxing */
    pinMuxReg->KICKER0 = 0x83E70B13U;
    pinMuxReg->KICKER1 = 0x95A4F1E0U;

    pinMuxReg->PINMUX[0] = PINMUX_BALL_N19_MII_RX_ER | PINMUX_BALL_D4_EMIF_ADDR_00 | PINMUX_BALL_D5_EMIF_ADDR_01 | PINMUX_BALL_C4_EMIF_ADDR_06;

    pinMuxReg->PINMUX[1] = PINMUX_BALL_C5_EMIF_ADDR_07 | PINMUX_BALL_C6_EMIF_ADDR_08 | PINMUX_BALL_C7_EMIF_ADDR_09 | PINMUX_BALL_C8_EMIF_ADDR_10;

    pinMuxReg->PINMUX[2] = PINMUX_BALL_C9_EMIF_ADDR_11 | PINMUX_BALL_C10_EMIF_ADDR_12 | PINMUX_BALL_C11_EMIF_ADDR_13 | PINMUX_BALL_C12_EMIF_ADDR_14;

    pinMuxReg->PINMUX[3] = PINMUX_BALL_C13_EMIF_ADDR_15 | PINMUX_BALL_D14_EMIF_ADDR_16 | PINMUX_BALL_C14_EMIF_ADDR_17 | PINMUX_BALL_D15_EMIF_ADDR_18;

    pinMuxReg->PINMUX[4] = PINMUX_BALL_C15_EMIF_ADDR_19 | PINMUX_BALL_C16_EMIF_ADDR_20 | PINMUX_BALL_C17_EMIF_ADDR_21;

    pinMuxReg->PINMUX[5] = 0U;

    pinMuxReg->PINMUX[6] = 0U;

    pinMuxReg->PINMUX[7] = 0U;

    pinMuxReg->PINMUX[8] = PINMUX_BALL_D16_EMIF_BA_1;

    pinMuxReg->PINMUX[9] = PINMUX_BALL_R4_EMIF_nCAS | PINMUX_BALL_N17_EMIF_nCS_0 | PINMUX_BALL_L17_EMIF_nCS_2;

    pinMuxReg->PINMUX[10] = PINMUX_BALL_K17_EMIF_nCS_3 | PINMUX_BALL_M17_EMIF_nCS_4 | PINMUX_BALL_R3_EMIF_nRAS | PINMUX_BALL_P3_EMIF_nWAIT;

    pinMuxReg->PINMUX[11] = PINMUX_BALL_D17_EMIF_nWE | PINMUX_BALL_E9_EMIF_ADDR_05 | PINMUX_BALL_E8_EMIF_ADDR_04 | PINMUX_BALL_E7_EMIF_ADDR_03;

    pinMuxReg->PINMUX[12] = PINMUX_BALL_E6_EMIF_ADDR_02 | PINMUX_BALL_E13_EMIF_BA_0 | PINMUX_BALL_E12_EMIF_nOE | PINMUX_BALL_E11_EMIF_nDQM_1;

    pinMuxReg->PINMUX[13] = PINMUX_BALL_E10_EMIF_nDQM_0 | PINMUX_BALL_K15_EMIF_DATA_00 | PINMUX_BALL_L15_EMIF_DATA_01 | PINMUX_BALL_M15_EMIF_DATA_02;

    pinMuxReg->PINMUX[14] = PINMUX_BALL_N15_EMIF_DATA_03 | PINMUX_BALL_E5_EMIF_DATA_04 | PINMUX_BALL_F5_EMIF_DATA_05 | PINMUX_BALL_G5_EMIF_DATA_06;

    pinMuxReg->PINMUX[15] = PINMUX_BALL_K5_EMIF_DATA_07 | PINMUX_BALL_L5_EMIF_DATA_08 | PINMUX_BALL_M5_EMIF_DATA_09 | PINMUX_BALL_N5_EMIF_DATA_10;

    pinMuxReg->PINMUX[16] = PINMUX_BALL_P5_EMIF_DATA_11 | PINMUX_BALL_R5_EMIF_DATA_12 | PINMUX_BALL_R6_EMIF_DATA_13 | PINMUX_BALL_R7_EMIF_DATA_14;

    pinMuxReg->PINMUX[17] = PINMUX_BALL_R8_EMIF_DATA_15 | PINMUX_BALL_R9_EXTCLKIN2 | PINMUX_BALL_R10_ETMTRACECLKOUT | PINMUX_BALL_R11_ETMTRACECTL;

    pinMuxReg->PINMUX[18] = PINMUX_BALL_B15_FRAYTX1 | PINMUX_BALL_B8_FRAYTX2 | PINMUX_BALL_B16_FRAYTXEN1 | PINMUX_BALL_B9_FRAYTXEN2;

    pinMuxReg->PINMUX[19] = PINMUX_BALL_C1_GIOA_2 | PINMUX_BALL_E1_GIOA_3 | PINMUX_BALL_B5_GIOA_5 | PINMUX_BALL_H3_GIOA_6;

    pinMuxReg->PINMUX[20] = PINMUX_BALL_M1_GIOA_7 | PINMUX_BALL_F2_GIOB_2 | PINMUX_BALL_W10_GIOB_3 | PINMUX_BALL_J2_GIOB_6;

    pinMuxReg->PINMUX[21] = PINMUX_BALL_F1_GIOB_7 | PINMUX_BALL_R2_MII_TXD_2 | PINMUX_BALL_F3_MII_COL | PINMUX_BALL_G3_MDIO;

    pinMuxReg->PINMUX[22] = PINMUX_BALL_J3_MIBSPI1NCS_3 | PINMUX_BALL_G19_MII_RXD_2 | PINMUX_BALL_V9_MIBSPI3CLK | PINMUX_BALL_V10_MIBSPI3NCS_0;

    pinMuxReg->PINMUX[23] = PINMUX_BALL_V5_MDCLK | PINMUX_BALL_B2_MIBSPI3NCS_2 | PINMUX_BALL_C3_MIBSPI3NCS_3 | PINMUX_BALL_W9_MIBSPI3NENA;

    pinMuxReg->PINMUX[24] = PINMUX_BALL_W8_MIBSPI3SIMO | PINMUX_BALL_V8_MIBSPI3SOMI | PINMUX_BALL_H19_MII_TXEN | PINMUX_BALL_E19_MIBSPI5NCS_0;

    pinMuxReg->PINMUX[25] = PINMUX_BALL_B6_MIBSPI5NCS_1 | PINMUX_BALL_W6_MIBSPI5NCS_2 | PINMUX_BALL_T12_MIBSPI5NCS_3 | PINMUX_BALL_H18_MII_RXD_3;

    pinMuxReg->PINMUX[26] = PINMUX_BALL_J19_MII_TXD_1 | PINMUX_BALL_E16_MIBSPI5SIMO_1 | PINMUX_BALL_H17_MIBSPI5SIMO_2 | PINMUX_BALL_G17_MIBSPI5SIMO_3;

    pinMuxReg->PINMUX[27] = PINMUX_BALL_J18_MII_TXD_0 | PINMUX_BALL_E17_MIBSPI5SOMI_1 | PINMUX_BALL_H16_MIBSPI5SOMI_2 | PINMUX_BALL_G16_MIBSPI5SOMI_3;

    pinMuxReg->PINMUX[28] = PINMUX_BALL_K18_MIBSPI4CLK | PINMUX_BALL_V2_MIBSPI4NENA | PINMUX_BALL_W5_MIBSPI4SIMO | PINMUX_BALL_U1_MIBSPI4NCS_0;

    pinMuxReg->PINMUX[29] = PINMUX_BALL_B12_MIBSPI4NCS_1 | PINMUX_BALL_V6_MIBSPI4SOMI | PINMUX_BALL_W3_SCI3RX | PINMUX_BALL_T1_N2HET1_07;

    pinMuxReg->PINMUX[30] = PINMUX_BALL_E18_MII_TXD_3 | PINMUX_BALL_V7_N2HET1_09 | PINMUX_BALL_D19_MII_TX_CLK | PINMUX_BALL_E3_N2HET1_11;

    pinMuxReg->PINMUX[31] = PINMUX_BALL_B4_MII_CRS | PINMUX_BALL_N2_SCI3TX | PINMUX_BALL_N1_N2HET1_15 | PINMUX_BALL_A4_N2HET1_16;

    pinMuxReg->PINMUX[32] = PINMUX_BALL_A13_SCI4RX | PINMUX_BALL_J1_N2HET1_18 | PINMUX_BALL_B13_SCI4TX | PINMUX_BALL_P2_N2HET1_20;

    pinMuxReg->PINMUX[33] = PINMUX_BALL_H4_N2HET1_21 | PINMUX_BALL_B3_N2HET1_22 | PINMUX_BALL_J4_N2HET1_23 | PINMUX_BALL_P1_MII_RXD_0;

    pinMuxReg->PINMUX[34] = PINMUX_BALL_A14_MII_RXD_1 | PINMUX_BALL_K19_MII_RXCLK | PINMUX_BALL_B11_MII_RX_DV | PINMUX_BALL_D8_N2HET2_01;

    pinMuxReg->PINMUX[35] = PINMUX_BALL_D7_N2HET2_02 | PINMUX_BALL_D3_MIBSPI2NENA | PINMUX_BALL_D2_MIBSPI2SOMI | PINMUX_BALL_D1_MIBSPI2SIMO;

    pinMuxReg->PINMUX[36] = PINMUX_BALL_P4_LIN2RX | PINMUX_BALL_T5_LIN2TX /*| PINMUX_BALL_T4_MII_RXCLK | PINMUX_BALL_U7_MII_TX_CLK*/;

    pinMuxReg->PINMUX[37] = PINMUX_BALL_E2_MIBSPI2CLK | PINMUX_BALL_N3_MIBSPI2NCS_0;

    pinMuxReg->PINMUX[80] = (SIGNAL_AD2EVT_T10 | 0x02020200U);

    pinMuxReg->PINMUX[81] = 0x02020202U;

    pinMuxReg->PINMUX[82] = 0x02020202U;

    pinMuxReg->PINMUX[83] = (SIGNAL_GIOA_0_A5 | 0x00020202U);

    pinMuxReg->PINMUX[84] = SIGNAL_GIOA_1_C2 | SIGNAL_GIOA_2_C1 | SIGNAL_GIOA_3_E1 | SIGNAL_GIOA_4_A6;

    pinMuxReg->PINMUX[85] = SIGNAL_GIOA_5_B5 | SIGNAL_GIOA_6_H3 | SIGNAL_GIOA_7_M1 | SIGNAL_GIOB_0_M2;

    pinMuxReg->PINMUX[86] = SIGNAL_GIOB_1_K2 | SIGNAL_GIOB_2_B9 |/* SIGNAL_GIOB_3_W10 |*/ SIGNAL_GIOB_4_G1;

    pinMuxReg->PINMUX[87] = SIGNAL_GIOB_5_G2 | SIGNAL_GIOB_6_J2 | SIGNAL_GIOB_7_F1 | SIGNAL_MDIO_G3;

    pinMuxReg->PINMUX[88] = (SIGNAL_MIBSPI1NCS_4_U10 | SIGNAL_MIBSPI1NCS_5_U9 | 0x00020000U) ;

    pinMuxReg->PINMUX[89] = SIGNAL_MII_COL_F3 | SIGNAL_MII_CRS_B4;

    pinMuxReg->PINMUX[90] = SIGNAL_MII_RX_DV_B11 | SIGNAL_MII_RX_ER_N19 | SIGNAL_MII_RXCLK_K19 | SIGNAL_MII_RXD_0_P1;

    pinMuxReg->PINMUX[91] = SIGNAL_MII_RXD_1_A14 | SIGNAL_MII_RXD_2_U3 | SIGNAL_MII_RXD_3_V3 | SIGNAL_MII_TX_CLK_D19;

    pinMuxReg->PINMUX[92] = /*SIGNAL_N2HET1_17_F3 | SIGNAL_N2HET1_19_G3 |*/ SIGNAL_N2HET1_21_H4 | SIGNAL_N2HET1_23_J4;

    pinMuxReg->PINMUX[93] = SIGNAL_N2HET1_25_M3 | SIGNAL_N2HET1_27_A9 | SIGNAL_N2HET1_29_A3 | SIGNAL_N2HET1_31_J17;

    pinMuxReg->PINMUX[94] = SIGNAL_N2HET2_00_D6 | SIGNAL_N2HET2_01_D8 | SIGNAL_N2HET2_02_D7 /*| SIGNAL_N2HET2_03_E2*/;

    pinMuxReg->PINMUX[95] = SIGNAL_N2HET2_04_D13 | SIGNAL_N2HET2_05_D12 | SIGNAL_N2HET2_06_D11 /*| SIGNAL_N2HET2_07_N3*/;

    pinMuxReg->PINMUX[96] = SIGNAL_N2HET2_08_K16 | SIGNAL_N2HET2_09_L16 | SIGNAL_N2HET2_10_M16 | SIGNAL_N2HET2_11_N16;

    pinMuxReg->PINMUX[97] = SIGNAL_N2HET2_12_V6 |/* SIGNAL_N2HET2_13_D2 |*/ SIGNAL_N2HET2_14_T1 | SIGNAL_N2HET2_15_K4;

    pinMuxReg->PINMUX[98] = SIGNAL_N2HET2_16_L4 | SIGNAL_N2HET2_18_N4 | /*SIGNAL_N2HET2_20_N2 |*/ SIGNAL_N2HET2_22_T7;

    pinMuxReg->PINMUX[99] = /*SIGNAL_nTZ1_1_N19 |*/ SIGNAL_nTZ1_2_F1 | SIGNAL_nTZ1_3_J3;


    pinMuxReg->PINMUX[161] = 0x02020200U;

    pinMuxReg->PINMUX[162] = 0x02020202U;

    pinMuxReg->PINMUX[163] = 0x00020202U;


    /* USER CODE BEGIN (3) */
    /* USER CODE END */

    PINMUX_EMIF_OUTPUT_ENABLE(ON);
    PINMUX_GATE_EMIF_CLK_ENABLE(ON);

    PINMUX_GIOA_DISABLE_HET1_ENABLE(OFF);
    PINMUX_GIOB_DISABLE_HET2_ENABLE(OFF);
    PINMUX_ETHERNET_SELECT(MII);
    PINMUX_ALT_ADC_TRIGGER_SELECT(1);


    PINMUX_ETPWM1_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM2_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM3_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM4_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM5_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM6_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM7_EQEPERR_ENABLE(EQEPERR12);
    PINMUX_ETPWM_TIME_BASE_SYNC_ENABLE(OFF);
    PINMUX_ETPWM_TZ1_ENABLE(ASYNC);
    PINMUX_ETPWM_TZ2_ENABLE(ASYNC);
    PINMUX_ETPWM_TZ3_ENABLE(ASYNC);
    PINMUX_ETPWM_EPWM1SYNCI_ENABLE(ASYNC);

    PINMUX_ETPWM_SOC1A_ENABLE(ON);
    PINMUX_ETPWM_SOC2A_ENABLE(ON);
    PINMUX_ETPWM_SOC3A_ENABLE(ON);
    PINMUX_ETPWM_SOC4A_ENABLE(ON);
    PINMUX_ETPWM_SOC5A_ENABLE(ON);
    PINMUX_ETPWM_SOC6A_ENABLE(ON);
    PINMUX_ETPWM_SOC7A_ENABLE(ON);

    PINMUX_EQEP1A_FILTER_ENABLE(OFF);
    PINMUX_EQEP1B_FILTER_ENABLE(OFF);
    PINMUX_EQEP1I_FILTER_ENABLE(OFF);
    PINMUX_EQEP1S_FILTER_ENABLE(OFF);
    PINMUX_EQEP2A_FILTER_ENABLE(OFF);
    PINMUX_EQEP2B_FILTER_ENABLE(OFF);
    PINMUX_EQEP2I_FILTER_ENABLE(OFF);
    PINMUX_EQEP2S_FILTER_ENABLE(OFF);

    PINMUX_ECAP1_FILTER_ENABLE(OFF);
    PINMUX_ECAP2_FILTER_ENABLE(OFF);
    PINMUX_ECAP3_FILTER_ENABLE(OFF);
    PINMUX_ECAP4_FILTER_ENABLE(OFF);
    PINMUX_ECAP5_FILTER_ENABLE(OFF);
    PINMUX_ECAP6_FILTER_ENABLE(OFF);

    PINMUX_GIOA0_DMA_ENABLE(ON);
    PINMUX_GIOA1_DMA_ENABLE(ON);
    PINMUX_GIOA2_DMA_ENABLE(ON);
    PINMUX_GIOA3_DMA_ENABLE(ON);
    PINMUX_GIOA4_DMA_ENABLE(ON);
    PINMUX_GIOA5_DMA_ENABLE(ON);
    PINMUX_GIOA6_DMA_ENABLE(ON);
    PINMUX_GIOA7_DMA_ENABLE(ON);
    PINMUX_GIOB0_DMA_ENABLE(ON);
    PINMUX_GIOB1_DMA_ENABLE(ON);
    PINMUX_GIOB2_DMA_ENABLE(ON);
    PINMUX_GIOB3_DMA_ENABLE(ON);
    PINMUX_GIOB4_DMA_ENABLE(ON);
    PINMUX_GIOB5_DMA_ENABLE(ON);
    PINMUX_GIOB6_DMA_ENABLE(ON);
    PINMUX_GIOB7_DMA_ENABLE(ON);

    pinMuxReg->PINMUX[174] |= (uint32_t)(~(0XFEFFFFFFU));

    PINMUX_TEMP1_ENABLE(OFF);
    PINMUX_TEMP2_ENABLE(OFF);
    PINMUX_TEMP3_ENABLE(OFF);

    /* Disable Pin Muxing */
    pinMuxReg->KICKER0 = 0x00000000U;
    pinMuxReg->KICKER1 = 0x00000000U;


    }

    2.I added the code:

    MRC p15, #0, R1, c1, c0, #0 ; Read System Control Register configuration data
    BIC R1, R1, #0x1 <<12 ; instruction cache disable
    BIC R1, R1, #0x1 <<2 ; data cache disable
    DSB
    MCR p15, #0, R1, c1, c0, #0 ; disabled cache RAMs ISB

    in the file :HL_sys_core.asm

    3.Here is the clock:

    The three solutions don't work.

  • Hello,

    I am sorry I don't have plan to review the source code of your pinmux settings.

    1. If you use TI Launchpad: please follow the instructions
    processors.wiki.ti.com/.../LAUNCHXL2_RM57L:_lwIP_Demo

    2. If you use TI HDK, Please use alternate pins instead of default pins (right column of input pin muxing in HALCoGen)

    3. If you use your own board, please pinmux the pins based on emac signals used in your board schematics