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TMS570LC4357: SPI/MibSPI connection to TPS65381A-Q1

Vincent LORENTZ
Intellectual 320 points

Part Number: TMS570LC4357
Other Parts Discussed in Thread: TPS65381A-Q1

Dear Support,

I am confused after having read the SLVSDJ1A (Datasheet of the TPS65381A-Q1) voltage safety supervisor for the TMS570LC4357. On page 103, it is mentioned that the TMS570 communicates with the TPS over MibSPI 1, 3 or 5. Why should the other MibSPI 2 and 4 not be suited? I do not see any reason for this and would prefer to use MibSPI2 to do it. Could you explain the signification of this block diagram and further explain also why the Chip Selects seems also to be restricted to 3..0?

Finally, on page 34 there is another surprising statement in the NOTE: why is the SDO pin not high-Z when the DIAG_OUT MUX is enabled? I do not see any technical reason having the SDO pin low impedance when the CS is high. For what is this chosen configuration ny TI good for? I did not find any configuration until now in which it would help. But I am sure that there must be a reason. Where can I find the explanation?

Thanks in advance.

Best regards

Vincent

  • 0
    TI__Mastermind 49120 points
    Hello Vincent,

    TMS570LC43x has 5 instances of the multi-buffered SPI (MibSPI), so you can use either of these interfaces for the TPS65381A connection. Some other TMS570 MCUs only have three MiBSPI instances (MibSPI1/3/5) and two standard SPI interfaces (SPI2/4). This is most likely the reason for the "limitation" shown in the diagram. Please note that the diagram only shows an example of connections between the TMS570 and TPS parts.

    Check out this app note for more information on this interface: www.ti.com/.../spna176a.pdf

    As for the question about the state of SDO when DIAG_OUT MUX is enabled, please post your question on the TI Power Management team forum: e2e.ti.com/.../196

    Regards,
    Sunil