MCU EMI

Hi Bob,

The custom PCB works great up to 24vdc yet the ADC only on high EMI channels requires >400us settling to get true results. Bus voltage ADC samples >82vdc remain no problem and succeed >25us PWM triggering converter settling. How can that be no problem but using GPTM to trigger ADC samples on EMI channels require >400us settling? Something is causing the ADC to converter to misbehave and halt USB data transfer at the same time.

Yet three PWM generators keep going like it's no body's business. However GPTM edge counts go bonkers at the same time PWM is running motor flawlessly. Another GPTM 120Mhz clocked one shot creates the FOC commutation codes from those EMF samples @25us without a single fault. If EMI effects one GPTM it should effect all GMTM equally, right?

EVM channels were 6" wire distance from ADC input. Custom PCB has ferrite beads & 1 megohm series resistors added to EMI channels reduces transients, not block them. Past clamping channels Schottky +3v3 on EVM made no difference reducing transients peaks >4v. Perhaps an MOV might prove better than 1ns clamping 3v3 TVS? OnSemi support said their ESD 3v3 TVS would not clamp below 5v and we needed a TVS zener they no long make. How about TI do they make a fast 3v3 TVS clamps below +5v transinets?

Bob

Did you notice the publication date PDF 1999 is 20 years old? Noting custom PCB has similar gridding power distribution and DGND islands separated from AGND plane via SMT 20mohm ferrite prior to TPS73533 LDO, separating input from output grounds planes. Several connected DGND filled pours (top/bottom) placed two/opposite sides of MCU distribute power, +3v3 does not specifically resemble being multipoint in the gridding.

I can PM the schematic, PCB foil PDF's for TI to examine what might help the TM4C1294 peripherals behave better. How can TI expect anyone trust a 20 year old EMI document for Tiva TM4C1294 MCU? When it was produced seemingly nanometer CMOS dies were thing of fiction. If that were not true Stellaris LM3S series could have surpassed 50Mhz clock rates.

Yes, I noticed the document is 20 years old. The basic principles of reducing EMI have not changed (I have been doing this job for 38 years). We do not do schematic or layout reviews.

Hello bob,

Bob Crosby said:

You might consider using twisted pairs on your cables between the EVM and your board.

You have misunderstood EVM driven inverter already had 6" twisted wires, works without issues up to 165vdc. It is the custom PCB where the MCU mounted local to DC inverter, odder issues >24vdc supply occur.

Surely there is something can be done to reduce ADC/USB intrusion of PWM SNR and correct several issues one stone?

Bob Crosby said:

We do not do schematic or layout reviews

Then TI should provide the exact layout guide for layers the EVM used to accomplish that which was not published in TM4C1294 design guide. If that is truly the way EMI is effecting MCU but not the EVM, PCB layer prints should be released publicly as are all other RDK's provided TIDA Gerber layers prints.

Fairly sure a Gerber did not exist in 2015 when last visited EVM page. Removing MCU from EVM today, must be solid copper second layer under pads, solder was reluctant to flow via several heating methods. Seemingly VDD was an issue since it pulled down 3v3 LDO as if shorted, ended up cutting MCU from PCB via carbide wheel. VDD measured 185 ohms prior to excessively heating board around MCU. After removal cleaned all pins shinny and VDD to GND measured 0.4 ohms, no solder shorts between pins.

Layers below MCU seems to have shorted VDD to GND in the process of heating pins 395*C with hot air tool 20 minutes. Solder reflow added to all pins with iron 348*C, would start flowing start to solidify before iron tip reached other end. Tried that method side to side chipping corner plastic lift point. Roughly spent 1.5 hours to remove single MCU. Custom PCB with AGND foil under MCU bottom side takes less than 10 minutes to remove with hot air tool 150*C preheat, then ramp 335*C lifting carefully from corner.

Previous 1.5 hours to remove failed MCU is good reason to not have copper foil under footprint even on 2nd layer. Mumetal or copper shield bottom MCU plastic case would be far more effective to stop EMI. It would be worth the extra expense of MCU since PWM and other signals traces often run directly under the MCU plastic case. The nickel iron 0.025" thick Mumetal forms an amazing EMI block. Might test a piece under next MCU replacement of higher 105*C MCU version.

Copper adhesive backed tape may be lower cost alternative if that produces EMI shield in the 4 layer PCB:

https://www.ebay.com/itm/20mmA-30m-Coppper-Foil-EMI-Shielding-Self-Adhesive-Low-Impedance-Conductive-Tape/162587836006?_trkparms=aid%3D111001%26algo%3DREC.SEED%26ao%3D1%26asc%3D20160908105057%26meid%3D599682d3b05f4608adc1cf265be141d1%26pid%3D100675%26rk%3D1%26rkt%3D15%26sd%3D162587836006%26itm%3D162587836006&_trksid=p2481888.c100675.m4236&_trkparms=pageci%3Af826470a-20dd-11e9-b420-74dbd18083e9%7Cparentrq%3A86a73bef1680ab4dc4a4bf91fffc765b%7Ciid%3A1 

Bob Crosby said:

You might consider using twisted pairs on your cables between the EVM and your board

That was an older picture and had thought it the newer version with twisted wires. You were correct the PWM and EMF wires were twisted pair, EVM side GND of EMF wires were left un-connected.

BTW the EVM booster headers are all little antennas sticking up in the air. So it is difficult to understand how they escaped the very same EMI that plagues the custom PCB. My gut feeling is the proximity of MCU to high voltage source is the bigger issue at hand.