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TMS570LS3137: ADC#1:ERRATA SPNZ195G

Midhun M
Prodigy 230 points
Part Number: TMS570LS3137

Hi,

As per the errata spnz195G for "TMS570LS3137", "An offset error is introduced in the conversion result of any channel if a current is being injected into a shared input channel." , if the input voltage on a shared input ADC channel > VCCAD-0.3V and if there is an overlap for sampling windows of two ADCs.

Have few questions related to this errata, can you please clarify

1. Does this mean that in a design the input voltage to ADC shall be limited to VCCAD-0.3V to avoid this issue, if simultaneous sampling is required?

2. What will be impact if AC signal is applied instead of DC at the shared input ADC channel?

3. We have sinusoidal signals connected to "AD1IN0" for ADC1 and "AD1IN16_AD2IN0" for ADC2  shared channel, ADC1 and ADC2 samples data simultaneously, so as per the errata there will be additional offset in "AD1IN0" channel when "AD1IN16_AD2IN0" amplitude is > VCCAD-0.3V ?

Regards,

Midhun

  • 0
    TI__Mastermind 49120 points
    Hi Midhun,

    See comments below:

    1. Does this mean that in a design the input voltage to ADC shall be limited to VCCAD-0.3V to avoid this issue, if simultaneous sampling is required?

    >> Yes, limiting the input voltage to a value lower than VCCAD - 0.3V will significantly (exponentially) reduce the input leakage, which is the main cause of this error.

    2. What will be impact if AC signal is applied instead of DC at the shared input ADC channel?

    >> The issue will still be observed if the two ADCs are sampling simultaneously and the input voltage exceeds VCCAD - 0.3V.

    3. We have sinusoidal signals connected to "AD1IN0" for ADC1 and "AD1IN16_AD2IN0" for ADC2 shared channel, ADC1 and ADC2 samples data simultaneously, so as per the errata there will be additional offset in "AD1IN0" channel when "AD1IN16_AD2IN0" amplitude is > VCCAD-0.3V ?

    >> Yes, the increased leakage on the shared ADC1_16/ADC2_0 channel can cause an offset in the reading for ADC1_0 channel. Are both the ADCs triggered by the same event in your application? Are their sampling windows configured identically?

    Regards,
    Sunil
  • 0 in reply to Sunil Oak
    Prodigy 230 points
    Hi Sunil,

    Group-1 is configured in both ADC1 & ADC2 devices and hence, it is software triggered (Hardware trigger is possible only for Event group)
    ADC1 is triggered first and subsequently ADC2 as we'll update Group-1 selection register of ADC1 first and then we'll update Group-1 selection register of ADC2. Hence, there will be few cycles delay in ADC2 trigger.

    Could you please confirm if the issue (related to offset in case of simultaneous conversion) still persists even though both the ADC devices are not triggered at the same time?

    Regarding the additional offset, can you please provide an equation to estimate the offset on ADC1 channel due to voltage on ADC2 or what will be the typical/worst case offset value (AC/DC).

    Regards,
    Midhun
  • 0 in reply to Midhun M
    TI__Mastermind 49120 points
    Hi Midhun,

    Groups 1 and 2 can also be event-triggered, although they are software-triggered by default. Having these two ADCs software-triggered could make it less likely for them to have their sampling periods overlap, of course depending on the actual delay between the two triggers and the actual sampling time configuration. What are your sampling periods for ADC1 and ADC2 group1?

    We don't have and equation to calculate the offset expected to be caused by this issue.

    Regards,
    Sunil