TMS570LC4357: Question about SW Library STC1_COMPARE_SELFCHECK

Hello,

In SAFTEY Library 2.4.0., we want to use library SL_Seltest_STC function with testType= STC1_COMPARE_SELFCHECK.

boolean SL_SelfTest_STC  ( register SL_SelfTestType  testType,  
  register boolean  bMode,  
  register SL_STC_Config *  config  
 )


When we check the SW library and the TMS Technical manual, We observe a difference between both:


Description of SW Library :

Configure the clock divider register STCCLKDIV with parameter
   
Configure the interval count INTCOUNT in register STCGCR0 with parameter
Configure restart/continue RS_CNT in register STCGCR0 to 1
    
Enable the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register
            
Configure self-test run time out counter STCTPR[31:0] with parameter

Select both cores for self-test in parallel by setting STCGCR1[11:8] to 0

Enable STC run (STCGCR1[3:0]=0xA)
    
Put the CPU in idle mode by executing the CPU idle instruction.
asm(“ WFI”)


Description technical Reference Manual (Chapter 10.10)

"Step 1: Configure the interval count to 1 in STCGCR0 register.

Segment 0
Step 2: Enable the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register and kick off the
self-test by enabling the first interval of segment 0. On the completion of self-test, TEST_FAIL bit will

be set in the STCGSTAT register. Check if the FSEGID bits in the STCFSTAT register are set to 00.
Depending on the segment 0 configuration (parallel or individual cores), the CORE1_FAIL or
CORE2_FAIL bits would be set.
Step 3: Disable one or both of the SELF_CHECK_KEY and FAULT_INS bits in the STCSCSCR register.
Then restart the self-test by programming bit 0 of the STCGCR0 register to 1. On the completion of the
test, the TEST_FAIL bit will be cleared in the STCGSTAT register"


This is my questions :
1- In the technical reference manual it isn't mentioned that a reset is occured in step2. is it normal?
2- In the technical reference manual, what is the signification of "On the completion of self-test" in step2 : by seting STCSEGPLR[1:0] = 0x0 or by setting STCGCR1[3:0] = 0xA or BOTH?
3-  In SW Library, step3 of technical manual is not done to clear registers at the end of the test? Is it normal?

Best regards,

François