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TM4C1294KCPDT: 3v3 tolerant GPIO

Genatco
Guru 55913 points
Part Number: TM4C1294KCPDT

Hello,

Configure GPIO resistive divider per design guide VBUS values below makes input High logic < VDD*0.65 minimum for 5v signals. The actual voltage at divider center point is roughly 1.90v with a robust 5v peak drive signal. QEI uses PL1,2,3 configures WPU, makes no difference as STD configured pins. Potentiometer rule suggest 6.8k series 10k to ground for input (+4.975V), expected High logic value at GPIO pin (+2.4875v).  Why are PL inputs much lower voltage than even potentiometer rule predicts? Is there a better way to configure the input or perhaps sensor output signals are OD with 10k pull up and effect the GPIO in undocumented way? 

What are better divider values since potentiometer rule values also will produce incorrect logic voltages for square wave input signals PHA, PHB, Index?

Design guide: A 5.6KΩ +/- 5% in series with a 10KΩ +/- 5% resistor should be wired as a voltage divider between VBUS on the connector and ground. This circuit drops the 5V VBUS value to 3.2V at the GPIO pin.

  • 0
    TI__Guru 72500 points
    Ohm's Law does work. Perhaps there is a current path that was not taken into account. Can you provide a more clear description of the circuit you are trying to measure? Perhaps in a schematic. I am having trouble following your text description above.
  • 0 in reply to Bob Crosby
    Guru 55913 points
    Since posting have ran Tina analysis that indicates voltage should indeed be close to 2.487v at the GPIO port. Have since discovered 10k to GND pulls down voltage of weak current drive (PHA/B) signals to 2.9v at the input divider (5.7k) thus 1.9v occurred at GPIO port. The QEI driver in motor sources 23ma @+5vdc.

    Tested the QEI sensor in motor can use +3v3 still produce PHA/B signals even though connector data sheet shows +5v. It would seem the divider in not required but 100 ohms series resistor, small decoupling cap would not hurt.