Hi there,
During PBIT following MCU power-up reset driven by nPORRST, I need to to perform nERROR pin integrity testing. This pin signal is latched by some logic to generate a low-pulse to nRST in order to warm-reset the MCU. I need to know the nERROR pin state (which should now be low) on the next power-up via ESMEPSR, in order NOT to re-perform this same test.
The nRST status saved in the SYSESR[3], bit EXTRST is not enough for my usage, because I have another watchdog test that is also connected to nRST.
To this end, I would like to understand more in order to select one of the following methods:
Method 1) Write 0x5 to the ESMEKR register in order to generate a low-pulse at the nERROR pin for the time defined in the low-time counter LTC, max at 1.3ms with a 50MHz VCLK (note the reset latching logic will generate a reset pulse of 25µs to warm-reset the MCU).
Method 2) Write 0xA to the ESMEKR register in order to let the nERROR low signal stays on indefinitely, and on next nRST, check back that ESMEPSR=0x0, then manually reset the ESMEKR content back to 0x5, then 0x0, and carries on with other tasks.
Questions now:
1) With method 1, I'm worrying how long the MCU would take in order to go back to the nERROR test routine, which is the sum of the MCU reset ramp up time plus the number of instructions to the nERROR test routine. If this delay is longer then 1.3ms, then this method is not good. What is the MCU reset ramp up time of the TMS570LS3137 before it start executing user code?
2) Is the described method 2 a workable solution? Asking this because examples in the TRM didn't use the 0xA value at all.
Thank you!
