TM4C123GH6PM: Hibernate module write/read timing

Part Number: TM4C123GH6PM

In section 7.3.1 of the TM4C datasheet (Register Access Timing), the timing requirement is described like so:

"...hibernation registers must be written only with a timing gap between accesses... software must guarantee that this delay is inserted between back-to-back writes to Hibernation registers or between a write followed by a read."

Given that reads are normally performed at the full peripheral clock rate (not requiring any delays to be inserted), I'm wondering if it's possible to read different hibernation registers after a write to one register, without waiting for WRC or any similar delay mechanism. It's quite clear that reading back the same register without waiting will fail, but could a different register be read? Here's what I'm trying to do (this is in an ISR):

/* Read the masked interrupt status. */
ulStatus = HibernateIntStatus(true);

HibernateIntClear(ulStatus)

/* Get the current match (the time that triggered this interrupt). */
ulMatchS = HibernateRTCMatchGet(0);

As it stands, the HibernateIntClear call busy-waits on the WRC bit before returning, and I've measured a significant time penalty in the ISR due to this call.

Can I read from that match register (or any hibernate register which is NOT HIB_IC, the one being written to) without waiting for WRC? I'd like to defer checking for WRC until it's absolutely necessary, if possible, and I do realize that means venturing away from driverlib.

Thanks!