TMS570LS3137: How to enable SRAM ECC checking in the CPU

Hello,

I understand that one can configure the CPU ATCM ECC checking feature of all Flash array (banks 0-6) with the ARM p15 register as per instructions of Enable TRM spnu499c para. 2.2.3.2, and pass any event generated to the Flash wrapper by setting the PMNC bit.

How can one enable the SRAM ECC checking feature?

Please provide link to the TRM.

Thank you.