Baffled what should be 400us Oneshot (GPTM4) delay with TAOTE trigger of SS2 ends up being only 9.8us. GPTM4 uses 120mHz SYSCLK loads IALR 0xBB80 (48000 ticks) monitored by GPIO PM3 bit toggles.
Set PM3 high during load of TAILR register then enable Oneshot during every PWM0 output six (80us) periods. Should delay SS2 trigger for 400us yet oddly GPIO PM3 bit clears during SS2 interrupt handling every 9.8us. Appears GPTM4 value is being reloaded every 9.8us even though it has not delayed the full count of 48000 ticks it was originally set for.
Why would GPTM4 allow TAILR register reloads prior to it's timeout event when it is configured for Oneshot mode via Tivaware call? Why are 48000 ticks only 9.8us Oneshot events if TAILR is not being reloaded each 80us period when SYSCLK is reported as 120 MHz? Expecting PM3 to stay high 400us but only pulses high roughly 0.1us, lots of ringing in the pulses edges.
Noted: Monitoring PM4 with scope probe, software interrupt was past configured for PM3.
/* OneShot Timer-4A/B 32 bit triggers ADC0-SS2
* sample blanking delay INA240 output settling time */
MAP_TimerClockSourceSet(TIMER4_BASE, TIMER_CLOCK_SYSTEM);
MAP_TimerConfigure(TIMER4_BASE, TIMER_CFG_ONE_SHOT);
/* Trigger ADC0 SS2 INA240 samples on GPTM timeout event */
HWREG(TIMER4_BASE + TIMER_O_ADCEV) |= TIMER_ADCEV_TATOADCEN;
/* Set TAOTE bit (GPTMCTL), enable GPTM ADC0 trigger */
HWREG(TIMER4_BASE + TIMER_O_CTL) |= TIMER_CTL_TAOTE;
/* Set IMR interrupt disabled for timeout events */
MAP_TimerIntDisable(TIMER4_BASE, TIMER_TIMA_TIMEOUT);
/* Enabled after PWMnENABLE register output events */
MAP_TimerDisable(TIMER4_BASE, TIMER_A);
/* No interrupt required for PWM triggered event */
MAP_IntDisable(INT_TIMER4A);
