In the Datasheet the Mode 0 timing diagram indicates that Master sets the O/P valid data at falling edge of SCK and also at the same time samples the input on very same falling edge. But the standard SPI has a opposite definition, i.e. the Master sets the O/P valid data at first rising edge of SCK and on or shortly after that also samples the I/P on same rising edge.
Please clarify as to why difference in protocol from standard SPI mode protocol or is it an error?
Regards,
Ahmed.
