• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 31 subscribers
  • Views 1347 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS570LS3137: CCM-R4F: Self-test, Error Forcing & Self-Test Error Forcing Mode interruptable?

Semir Spahic
Prodigy 60 points
Part Number: TMS570LS3137
Other Parts Discussed in Thread: HALCOGEN

Hi,

I am trying to use the ccmSelfCheck() function (generated in Halcogen) for the CCM Self-test.

When I perform the Self-test without handling the interrupts generated by the ESM (low level for the flag "CCM-R4F self-test error" and high level for "CCM-R4F - compare") the self-test passes correctly (the self-test, error forcing and self-test error forcing).

But now when I try to implement some handling for the low level interrupt when the "CCM-R4F self-test error" flag gets set the self-test never finishes. To be more precise, when the CCM is configured in the CCM Error forcing mode (CCMKEYR = 0x9U) the low level interrupt gets triggered and after that the self-test doesn't proceed (it is a bit hard to know what really happens since it is not possible to be in debug mode because of the CCM but i certainly know that the execution of the code doesn't get further than "while (CCMKEYR != 0U) {}").

In the function that handles the low level interrupt I am just setting a Pin to high for test purposes so I am not even clearing the ESM flag. I am not sure what happens when the high level interrupt gets handeld since that is not working yet even though I am sure the "CCM-R4F - compare" flag gets also set since I tested the ERROR pin after entering the Error forcing mode and it becomes low for a short period of time.

My question:

Is it possible that the Self-test of the CCM isn't interruptable? Would that mean that I have to dissable the IRQ and FIQ before I start the ccmSelfCheck() function and later enable it since our plan is to perform this self-test periodicaly in our application?

Thanks in advance.

  • 0
    TI__Mastermind 21425 points
    Hello Semir,
    Did you disconnect your debugger from the target, while running this test?

    Best regards,
    Miro
  • 0 in reply to Miro
    Prodigy 60 points
    Hello Miroslav,

    the debugger is physically attached to the target but I'm not in debug mode. Since the test completes successfully when I don't handle the ESM-generated interrupts I assume leaving the debugger attached is OK in accordance to 9.3.5 in TRM (Operation During CPU Debug Mode).

    Regards,
    Semir Spahic
  • 0 in reply to Semir Spahic
    TI__Mastermind 21425 points
    Hello,
    Could you try with disconnected debugger?

    Best regards,
    Miro
  • 0 in reply to Miro
    Prodigy 60 points
    Hello Miro,

    I've just tried with the debugger detached, I get the same result.

    But is it generaly ok to interrupt the CCM self-test and handle the interrupt generated by the ESM? If so, maybe the problem arises in my interrupt routine but I am not able to see that since I cannot be in the debug mode.

    Is there an easy way to generate an ESM Group 1 flag to trigger a low level interrupt in debug mode? That way I could see what happens after I handle the low level interrupt.

    Regards,
    Semir Spahic
  • 0 in reply to Semir Spahic
    TI__Mastermind 21425 points
    Hello,
    ESM Group 2 interrupts can not be disabled and they are High-Priority. CCM-R4F is assigned to ESM Group 2. I've just made a test and in esmGroup2Notification function I am calling gioSetBit to turn on user LED. LED goes on.

    Best regards,
    Miro
  • 0 in reply to Miro
    Prodigy 60 points
    Hello,

    OK. After your user LED goes on, does the self-test finish correctly?

    In my case after I come back form the interrupt routine the self-test stops.

    Best regards,
    Semir Spahic
  • 0 in reply to Semir Spahic
    Prodigy 60 points

    Hello,

    Now that my routine that is servicing the high-level interrupts also works I think that I found out what the problem is.

    The code-snippet that is relevant for this:

    When I configure the CCM in error forcing mode the Group 2 ESM flag gets set and my interrupt routine gets called. Now, if I don't clear the ESM flag that was set the interrupt routine gets called over and over again (I toggled a testpin in my routine to confirm that) and I got stuck. The correct thing to do is of course to clear the flag that triggered the interrupt and if I do that inside of my routine the self-test continues and in line 77 the condition checks if the right ESM flag was set since an error was forced but since we already cleared that bit in the interrupt routine this check fails and my self-test fails.

    Q:

    Is this self-test intended for use when the interrupts, that are being generated by the ESM, are handled? If so, then can this be done without changing the code generated by HALCOGEN? Any other suggestions?

    Thanks in advance,

    Semir Spahic

  • 0 in reply to Semir Spahic
    TI__Mastermind 21425 points
    Hello,
    Sorry for the late reply.
    The sequence generated by HALCoGen assumes that interrupts are not enabled when running this self-check of the CCM. If you clear the flag in the ISR, then you do not need to check if the flag was still set in the code sequence. Because there is no user code section generated by HALCoGen before check for the flag to be set, if you are using an interrupt to clear the self-test error flag, then the flag status check can be skipped. OR, you can use the HALCoGen code sequence as a reference, and write your own code routine.

    Best regards,
    Miro
  • 0 in reply to Miro
    Prodigy 60 points
    Hello Miro,

    I've already adjusted the ccmSelfTest() function generated by Halcogen and it works as expected. I also wanted to write a post so the issue can be closed but somehow forgot to do it.

    Thanks for answering nevertheless.

    Best regards,
    Semir Spahic