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LAUNCHXL2-TMS57012: nRST vs nPORRST behaviour after oscillator fault

Ritchie
Intellectual 290 points
Part Number: LAUNCHXL2-TMS57012

Dear TI community,

My question is related to the out-of-the-box demo that is present on the launchpad. When injecting the oscillator failure by shorting the jumper, the only way to recover from this fault is by pressing the nPORRST switch. All other faults from the demo (ECC, Core Compare) can be recovered from by pressing nRST which is warm reset.

Why pressing nRST after injecting an osc failure is not resetting the cpu/board? How and why the fault condition remains after pressing nRST switch and can be "cleared" only by pressing nPORRST switch?

Best Regards,

Ritchie

  • 0
    TI__Mastermind 21425 points
    Hello,
    The oscillator is enabled when nPORRST is low. While nPORRST, the oscilator and LPO are enabled and start-up by default. After nPORRST is released (goes high) the clock detect circuit begins to monitor the oscillator. If the oscillator is within valid range, the oscillator becomes the defaut clock for the device. If the oscillator is not in valid range, HF LPO is selected as a clock source.
    If the oscillator fails, then HF LPO is supplied to be clock source for the device.
    The automatic switch-over from oscillator to HF LPO allows the application to execute at a reduced frequency and respond to a problem with the external crystal/resonator.
    The oscillator may be re-enabled after fail with following procedure:
    1. Switch all clock domains from the oscillator to the HF LPO (for example, GHVSRC uses HF LPO, VCLKAn uses HF LPO or VCLK, and so on).
    2. If the PLL is used, disable the PLL by setting the appropriate bit in the Clock Source Disable Set Register (CSDISSET) of the System and Peripheral Control Registers.
    3. Disable the oscillator by setting the appropriate bit in the Clock Source Disable Set Register (CSDISSET). This action resets the clock detect and allows the oscillator to propagate through GCM clock source 0.
    4. Re-enable the oscillator by setting the appropriate bit in the Clock Source Disable Clear Register (CSDISCLR) of the System and Peripheral Control Registers.
    5. Clear the OSCFAIL flag in the Global Status Register (GLBSTAT) by writing a 1 to the bit. The PLL slip bits may also be set on an oscillator failure. These can also be cleared.
    6. Switch the clock domains back to the oscillator.
    7. Re-enable the PLL by setting the appropriate bit in the Clock Source Disable Clear Register (CSDISCLR).

    For more details, please refer to Chapter 10 of device TRM ( www.ti.com/.../spnu515c.pdf ).

    Best regards,
    Miro
  • 0 in reply to Miro
    Intellectual 290 points
    I accidentally clicked Resolved, however it is still not clear to me why other faults can be cleared by nRST when the oscillator fault can only be cleared by nPORRST?
  • 0 in reply to Ritchie
    TI__Mastermind 21425 points
    Hello,
    "... While nPORRST, the oscilator and LPO are enabled and start-up by default. After nPORRST is released (goes high) the clock detect circuit begins to monitor the oscillator. If the oscillator is within valid range, the oscillator becomes the defaut clock for the device. If the oscillator is not in valid range, HF LPO is selected as a clock source."

    nRST does not restart clock detect procedure.

    Best regards,
    Miro