Other Parts Discussed in Thread: HALCOGEN
Tool/software: TI C/C++ Compiler
Hello Forum,
I am relatively new to ARM processors and trying to implement checking for RAM ECC on the fly for inserted errors. I read a lot of threads on this, but didn't find a solution for my case.
I ran upon this post: e2e.ti.com/.../774180
Having the same problem. Using code from HalcoGen doesn't work for me. But using the one from SPNA126 did bring me to some point. I am able to generate error on ESMSR3 on channel 3 but not on channel 5. I also followed the instructions from QJ Wang. I stumbled upon following, not sure if it is a problem: When i try to change 2 Bits via XOR, I noticed that somehow 16Bits get changed. (I am using IAR Workbench). See figures bellow. On first figure, before executing line 96 on, it is shown in Memory1 view, that at location 0x08400010 is 2e2e_2e2e written.
After hitting F11 (Step in) once, the value at given location changes into 2d2d_2d2d. I wanted to provoke a double bit error, not to change 16 bits.
Here is the code for the first function, the second one for B1TCM is called afterwards.
void checkRamEccB0TCM(void)
{
volatile uint64 ramread = 0U;
volatile uint32 regread = 0U;
uint64 tcramA2_bk = tcramA2bit;
uint64 tcramB2_bk = tcramB2bit;
/* Enable writes to ECC RAM, enable ECC error response */
tcram1REG->RAMCTRL = 0x0005010AU;
tcram2REG->RAMCTRL = 0x0005010AU;
// coreDisableRamEcc
asm("MRC p15,#0, r1, c1, c0, #1");
asm("MVN R0,#0x1<<26"); //; B0TCM ECC check disable
asm("AND R1 ,R1, R0");
asm("MVN R0,#0x1<<27"); //; B1TCM ECC check disable
asm("AND R1 ,R1,R0");
asm("DMB");
asm("MCR p15,#0, r1, c1, c0, #1");
asm("ISB"); // ; To ensure the write before proceeding
asm("MRC p15, #0, r1, c9, c12, #0");
asm("MVN R0,#0x00000010"); //; Disable export of the events in PMNC
asm("AND R1 ,R1,R0");
asm("DMB");
asm("MCR p15, #0, r1, c9, c12, #0");
asm("ISB"); //; To ensure the write before proceeding
/* Force a double bit error in both the banks */
//tcramA2bitError ^= (uint64_t)0x00000003U;
tcramA2bitError ^= 3U; //#define tcramA2bitError (*(volatile uint32 *)(0x08400010U))
// coreEnableRamEcc
asm("MRC p15,#0,r1,c9,c12,#0"); // Reading secondary Aux secondary Reg.
asm("ORR r1, r1, #0x00000010");
asm("DMB");
asm("MCR p15,#0,r1,c9,c12,#0"); //; Enable export of the events in PMNC
asm("ISB"); //; To ensure the write before proceeding
asm("MRC p15, #0, r1, c1, c0, #1");
asm("ORR r1, r1, #0x1 <<26"); //; B0TCM ECC Check Enable
// asm("ORR r1, r1, #0x1 <<27"); //; B1TCM ECC Check Enable
asm("DMB");
asm("MCR p15, #0, r1, c1, c0, #1");
asm("ISB");
/* Read the corrupted data to generate double bit error */
ramread = tcramA2bit;
regread = tcram1REG->RAMUERRADDR;
/* disable writes to ECC RAM */
tcram1REG->RAMCTRL = 0x0005000AU;
tcram2REG->RAMCTRL = 0x0005000AU;
/* Compute correct ECC */
tcramA2bit = tcramA2_bk;
tcramB2bit = tcramB2_bk;
}
Q1: Is it normal that 16Bits are changed, I wanted to change just 2.
Q2: Could this be the cause why I'm not getting the error on channel 5.
Additional note:
For B0TCM, data flow jumps into data abort handler of the bootloader and then changes to a data abort into the application where I do the handling of the error (reseting esmsr3).
For B1TCM, data flow again comes to data abort handler of the application, but when check for error is performed, there is none signaled in esmsr3. Value of esmsr3 is 0x00. should be 0x20. Also in addition, regarding change of bits. For this case, there are alse 16Bits changed, not just 2. I am using different locations in RAM ECC (0x08400010 and 0x08400018).
If the given Information is not sufficient, I can update it in example with more print screens with register values at different points at debbug time.
Regards,
Mensur
