Other Parts Discussed in Thread: HALCOGEN,
Hello Community,
I am currently migrating my project from the TI compiler (v16.9.6.LTS) to GCC (so I selected GNU v6.3.1 Linaro) in CCS. After exporting the HALCoGen files (with FreeRTOS), I started noticing some Cortex-r4 references, when the RM57 MCU has a Cortex-r5 processor. For example, in the HL_ajsm.s file:
.syntax unified
.cpu cortex-r4
.arm
.section .ajsm,"a",%progbits
AJSM0: .word 0xA5E16BC6
AJSM1: .word 0x837706ED
AJSM2: .word 0x4DD09BA4
AJSM3: .word 0x03C607AC
I also noticed that in the linker file (HL_sys_link.ld) the highest stack address is set to 0x08040000, allowing for 256K of RAM, when the RM57 has 512K:
/* Highest address of the stack */
_estack = 0x8040000; /* end of 256K RAM */
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x400; /* required amount of heap */
/* Specify the memory areas */
MEMORY
{
VECTORS(rx) : ORIGIN = 0x00000000, LENGTH = 0x00000020
KERNEL (rx) : ORIGIN = 0x00000020, LENGTH = 0x00008000
FLASH (rx) : ORIGIN = 0x00008020, LENGTH = (0x001F7FE0 + 0x00200000)
CPU_STACK (rw) : ORIGIN = 0x08000000, LENGTH = 0x00000800 /* Stack is configured in sys_core.asm */
KRAM (xrw) : ORIGIN = 0x08000800, LENGTH = 0x00000800
RAM (xrw) : ORIGIN = (0x08000800 + 0x00000800), LENGTH = (0x0007F800 - 0x00000800)
MEMORY_B1 (rx) : ORIGIN = 0x60000000, LENGTH = 0K
}
Seems like the HALCoGen code was generated for another board/processor even though I selected the RM57. Is there a way to get the correct HAL/FreeRTOS code?
Thank you,
Surialic
