RM57L843: RTI 4MHz interrupt issue

Hello,
If your ISR takes more than 250nsec then next interrupt will be pending until ISR is proceed.


Best regards,
Miro

Hi Miro
My ISR is taking around 950 nsec. The ISR code just toggles GPIO pin.Why the RTI driver is taking around 900nsec to trigger an interrupt.
Here is my ISR code
void rtiCompare0Interrupt(void)
{
/* USER CODE BEGIN (43) */
/* USER CODE END */

rtiREG1->INTFLAG = 1U;
gioToggleBit(gioPORTA, 7); //PI pin

/* USER CODE BEGIN (44) */
/* USER CODE END */
}
Main application code just loops in infinite while
while(1);

Hi Miro
My ISR is taking around 950 nsec. The ISR code just toggles GPIO pin.Why the RTI driver is taking around 900nsec to trigger an interrupt.
Here is my ISR code

void rtiCompare0Interrupt(void)
{
/* USER CODE BEGIN (43) */
/* USER CODE END */

rtiREG1->INTFLAG = 1U;
gioToggleBit(gioPORTA, 7); //PI pin

/* USER CODE BEGIN (44) */
/* USER CODE END */
}

Main application code is given below

int main(void)
{
/* USER CODE BEGIN (3) */


/* Initialize GPIO */
gioInit();

/* Initialize RTI driver */
rtiInit();


/* Set high end timer GIO port A pin direction to all output 1 -output : 0-input*/


gioSetDirection(gioPORTA, 0xFFFFFFFC);



gioEnableNotification(gioPORTA,0);




rtiEnableNotification(rtiREG1,rtiNOTIFICATION_COMPARE0);


/*Enable IRQ - Clear I flag in CPS register
Note: This is usually done by the OS or in an svc dispatcher*/
_enable_IRQ_interrupt_();

rtiResetCounter(rtiREG1,rtiCOUNTER_BLOCK0);
rtiResetCounter(rtiREG1,rtiCOUNTER_BLOCK1);


rtiStartCounter(rtiREG1,rtiCOUNTER_BLOCK0);

/* Start RTI Counter Block 0 for system ticks generation */
rtiStartCounter(rtiREG1,rtiCOUNTER_BLOCK1);



while(1);

}

RTI Init code:


void rtiInit(void)
{
/* USER CODE BEGIN (2) */
/* USER CODE END */
/** @b Initialize @b RTI1: */



/** - Setup timebase for free running counter 0 */
rtiREG1->TBCTRL = 0x00000000U;

/** - Enable/Disable capture event sources for both counter blocks */
rtiREG1->CAPCTRL = 0U | 0U;

/** - Setup input source compare 0-3 */
rtiREG1->COMPCTRL = 0x00000000U | 0x00000000U | 0x00000000U | 0x00000000U;

/** - Reset up counter 0 */
rtiREG1->CNT[0U].UCx = 0x00000000U;

/** - Reset free running counter 0 */
rtiREG1->CNT[0U].FRCx = 0x00000000U;

/** - Setup up counter 0 compare value
* - 0x00000000: Divide by 2^32
* - 0x00000001-0xFFFFFFFF: Divide by (CPUC0 + 1)
*/
rtiREG1->CNT[0U].CPUCx = 1U;

/** - Reset up counter 1 */
rtiREG1->CNT[1U].UCx = 0x00000000U;

/** - Reset free running counter 1 */
rtiREG1->CNT[1U].FRCx = 0x00000000U;

/** - Setup up counter 1 compare value
* - 0x00000000: Divide by 2^32
* - 0x00000001-0xFFFFFFFF: Divide by (CPUC1 + 1)
*/
rtiREG1->CNT[1U].CPUCx = 1U;

/** - Setup compare 0 value. This value is compared with selected free running counter. */
rtiREG1->CMP[0U].COMPx = 1U;

/** - Setup update compare 0 value. This value is added to the compare 0 value on each compare match. */
rtiREG1->CMP[0U].UDCPx = 1U;

/** - Setup compare 1 value. This value is compared with selected free running counter. */
rtiREG1->CMP[1U].COMPx = 1U;

/** - Setup update compare 1 value. This value is added to the compare 1 value on each compare match. */
rtiREG1->CMP[1U].UDCPx = 1U;

/** - Setup compare 2 value. This value is compared with selected free running counter. */
rtiREG1->CMP[2U].COMPx = 1U;

/** - Setup update compare 2 value. This value is added to the compare 2 value on each compare match. */
rtiREG1->CMP[2U].UDCPx = 1U;

/** - Setup compare 3 value. This value is compared with selected free running counter. */
rtiREG1->CMP[3U].COMPx = 1U;

/** - Setup update compare 3 value. This value is added to the compare 3 value on each compare match. */
rtiREG1->CMP[3U].UDCPx = 1U;

/** - Clear all pending interrupts */
rtiREG1->INTFLAG = 0x0007000FU;

/** - Disable all interrupts */
rtiREG1->CLEARINTENA = 0x00070F0FU;

/** - Setup NTU source, debug options and disable both counter blocks */
rtiREG1->GCTRL = (uint32)((uint32)0x5U << 16U) | 0x00000000U;

/** @note This function has to be called before the driver can be used.\n
* This function has to be executed in privileged mode.\n
* This function does not start the counters.
*/

/* USER CODE BEGIN (3) */
/* USER CODE END */
}

Hello,
When IRQ is generated, all other interrupts are pending (IRQ can be interrupted only by FIQ). If your ISR execution takes 950nsek than next IRQ will be generated in more than 950nsek.

Best regards,
Miro

Hi,

How can i bringdown the isr execution time from 950 nsec to 250nsec. A simple gpio pin toggling should not take 950 nsec.

Please suggest your ideas.

Thanks

Venkat

Hi,

Do you have any sample RTI driver code /HALCOGEN project which supports 4MHz and higher frequencies.

Thanks,

Venkat.