TMS570LC4357: Seamless leaving of DCAN Silent Mode

Hello,

Loop Back mode and Silent mode are different :

In Silent mode the DCAN will listen the Bus without sending any dominant bits (no ACK, No error Frames etc...), in this special mode the TEC/REC (Transmit Error counter/Receive Error counter) are Freeze.

In LoopBack mode you route the Tx pin to the Rx pin, in others word you only receive the message that you are transmitting.

You mentionned that after leaving Silent mode BusOff, Error Warrnig, Error Passive are set in the Error status registers,

Have you check  Before entering to silent mode whats is the Value of the Error Status ?

For my side i didn't expect any Modification of TEC/REC (which could lead to a ES change) during silent mode.

let me know the results,

BR,

Yacine

Hi Yacine,

Thanks for the reply. I'm aware that Loop Back mode is different than Silent Mode. I only mentioned Loop Back mode because there is a note in the Test Modes section of the TRM (spnu563, 27.14: "When using any of the Loop Back modes, it must be ensured by software that all message transfers are finished before setting the Init bit to ‘1’."). This note appears just before section 27.14.1 Silent Mode, so one could (mis-?)interpret the note there to apply to Silent Mode as well.

Before leaving silent mode, error status does not appear.

After leaving silent mode, error status sometimes appears after attempting the first transmit on a port.

Whether the error status appears or not, I have observed that the CAN Tx ISR is delayed by 5-10ms, in the period immediately after leaving silent mode, if we attempt to transmit CAN immediately after leaving silent mode.

Hello Ninja,

The CAN transfer starts when the CPU writes the message number the IFx command register. During transfer, the busy bit is set to 1 automatically. How do you measure the time between writing message number to ISR is triggered?

Hi QJ,

I'm measuring timing from writing the IF2 command register to the beginning of the ISR. Typically the timing is < 1ms, but in the problem case (transfers initiated immediately after leaving silent mode) it is 5ms-10ms.

Regarding the IF2 command register busy bit, I never see this bit go high, even immediately after writing the IF2 command register which results later in a successful Tx. If the bit stays high for 4 to 14 VBUS clock cycles, I should be able to see it high for many CPU cycles, but it's not the case. Does this indicate some problem?

Maybe my questions have become unfocused. Here are the main questions I have:

1) I don't see the IF2 command register busy bit ever get set, even when I check it immediately after writing the last 8 bits of the command register (even when I'm repeatedly transmitting CAN with no observed problems). Is this unexpected?

2) What could cause the Tx interrupt to become delayed, relative to writing the last 8 bits of the command register?

> What could cause the Tx interrupt to become delayed, relative to writing the last 8 bits of the command register?

Generalizing this, it seems to me that for some period of time after leaving silent mode (maybe < 100 ms), CAN transmit is not reliable. The transmit error counter may be incremented spuriously and we may incorrectly enter bus off.

Hello ninja,

Are you modifying for some reason the INIT bit (DCAN_CTL) ? when leaving/Entering the Silent mode ?

BR,

Yacine

Hi Yacine,

I have tried both ways with similar results:

1) Set INIT / CCE.

2) Wait for INIT bit to go high.

3) Update SILENT.

4) Clear CCE / INIT.

5_ Wait for INIT bit to go low.

.. and also simply:

1) Update SILENT (don't touch INIT / CCE).

According to my reading of the datasheet, it's not necessary to set INIT / CCE prior to modifying SILENT. But in either case, I still see the issue.