TMS570LC4357: SDRAM EMIF synchronous Memory switching

Needhu Gunasegaran

Intellectual 2890 points

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi QJ,

In the DS of TMS570LC4357, the minimum cycle time for the SDRAM Tc=10ns. (Table6-38.)

does this mean it corresponds to the EMIF-clk 100MHz?

The question comes from the following,

my customer set up the EMIF clock to 150 MHz in HalcoGen and they use the SDRAM device with Fclk @ 166MHz.

Is it ok?

Thanks,

Needhu

over 6 years ago

0 QJ Wang over 6 years ago

TI__Guru**** 196666 points

Hello Needhu,

Yes, the maximum EMIF clock is 100MHz. 150MHz is out of the spec. 166Mhz SDRAM can be used without any problem.

0 Needhu Gunasegaran over 6 years ago in reply to QJ Wang

TI__Intellectual 2890 points

Hi QJ,

Thanks for the feedback.

Do we have any documents explaining the usage of SDRAM at 166MHz?

Question that popped up is, why are we then able to configure the EMIF in Halcogen at 150MHz if it exceeds the specs?

Thanks,
Needhu

0 QJ Wang over 6 years ago in reply to Needhu Gunasegaran

TI__Guru**** 196666 points

Hello Needhu,

Please refer to the SDRAM datasheet.

Generally speaking, you can safely interface a faster memory with a slower memory clock.

EMIF uses VCLK3. The maximum clock rate for VCLK3 is 110MHz. The maximum clock for EMIF is 100MHz. I will check with HALCoGen team if adding a notes in clock setting page to shows the maximum EMIF clock. Thanks for pointing this out.

0 Needhu Gunasegaran over 6 years ago in reply to QJ Wang

TI__Intellectual 2890 points

QJ,
Thank you for the feedback.

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TMS570LC4357: SDRAM EMIF synchronous Memory switching